Cirrus Logic CS42518-CQZ Instructions Manual page 41

CS42518
Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decou-
pling capacitors are recommended. Decoupling capacitors should be as near to the pins of the CS42518
as possible. The low value ceramic capacitor should be the nearest to the pin and should be mounted on
the same side of the board as the CS42518 to minimize inductance effects. All signals, especially clocks,
should be kept away from the FILT+, VQ and LPFLT pins in order to avoid unwanted coupling into the
modulators and PLL. The FILT+ and VQ decoupling capacitors, particularly the 0.1 µF, must be positioned
to minimize the electrical path from FILT+ and REFGND. The CDB42518 evaluation board demonstrates
the optimum layout and power supply arrangements.
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