Clevo W740SU Service Manual page 50

Schematic Diagrams
Processor 5/7- Power
Sheet 7 of 42
Processor 5/7-
Power
B - 8 Processor 5/7- Power
5 4
V_VCCDDQ VDDQ
D02 short
1 2
PJ18 PJ18 C242 C242
*5mm *5mm *0.1u_10V_X5R_04 *0.1u_10V_X5R_04
C245 C245
*0.1u_10V_X5R_04 *0.1u_10V_X5R_04
D
V_VCCDDQ
VALUE
330uF_2.5V_6.6*6.6*4.2
(6-09-3371P-190)
C46 C46 C26 C26 C45 C45 C25 C25 C22 C22
+ + + +
10u_6.3V_X5R_06 10u_6.3V_X5R_06 10u_6.3V_X5R_06 10u_6.3V_X5R_06 10u_6.3V_X5R_06 10u_6.3V_X5R_06 390uF_2.5V_12m_6.6*6.6*4.2 390uF_2.5V_12m_6.6*6.6*4.2
390uF_2.5V_12m_6.6*6.6*4.2 390uF_2.5V_12m_6.6*6.6*4.2
C181 C181 C179 C179 C182 C182 C43 C43 C44 C44
10u_6.3V_X5R_06 10u_6.3V_X5R_06 10u_6.3V_X5R_06 10u_6.3V_X5R_06 10u_6.3V_X5R_06 10u_6.3V_X5R_06 10u_6.3V_X5R_06 10u_6.3V_X5R_06 10u_6.3V_X5R_06 10u_6.3V_X5R_06
C237 C237 C227 C227 C177 C177 C28 C28 C29 C29
*22u_6.3V_X5R_08 *22u_6.3V_X5R_08 *22u_6.3V_X5R_08 *22u_6.3V_X5R_08 *22u_6.3V_X5R_08 *22u_6.3V_X5R_08 *22u_6.3V_X5R_08 *22u_6.3V_X5R_08 *22u_6.3V_X5R_08 *22u_6.3V_X5R_08
C180 C180 C236 C236 C247 C247 C229 C229 C176 C176
1u_6.3V_X5R_04 1u_6.3V_X5R_04 1u_6.3V_X5R_04 1u_6.3V_X5R_04 1u_6.3V_X5R_04 1u_6.3V_X5R_04 1u_6.3V_X5R_04 1u_6.3V_X5R_04 1u_6.3V_X5R_04 1u_6.3V_X5R_04
C
C233 C233 C234 C234 C232 C232 C235 C235 C246 C246
1u_6.3V_X5R_04 1u_6.3V_X5R_04 1u_6.3V_X5R_04 1u_6.3V_X5R_04 1u_6.3V_X5R_04 1u_6.3V_X5R_04 1u_6.3V_X5R_04 1u_6.3V_X5R_04 1u_6.3V_X5R_04 1u_6.3V_X5R_04
R1 R1
VCCIO_OUT
R204 R204
VCCIO2PCH
VCCIOA_OUT
SVID Signals
VCCIO_OUT
R29 R29
35 H_CPU_SVIDALRT#
35 H_CPU_SVIDCLK
35 H_CPU_SVIDDAT
R30 R30 75_04 75_04 H_CPU_SVIDALRT#
H_CPU_SVIDCLK
R17 R17 *54.9_1%_04 *54.9_1%_04
R16 R16 130_1%_04 130_1%_04 H_CPU_SVIDDAT
B
1.05VS
R4 R4 150_1%_04 150_1%_04 PWR_DEBUG#
R570 R570
D01A add
*10K_04 *10K_04
1.05VS VCCIO_OUT
R9 R9 *0_06 *0_06
C3 C3
*4.7u_6.3V_X5R_06 *4.7u_6.3V_X5R_06
1.05VS VCCIO2PCH
A
R205 R205 0_06 0_06
C123 C123
*4.7u_6.3V_X5R_06 *4.7u_6.3V_X5R_06
5 4
3
Haswell Processor 5/7 ( POWER )
HASWELL_BGA_E HASWELL_BGA_E
U1E U1E
J17
RSVD VCC
J21
4.2A
RSVD VCC
J26
RSVD VCC
V_VCCDDQ J31
RSVD VCC
VCC
AR29
VDDQ VCC
AR31
VDDQ VCC
AR33
VDDQ VCC
AT13
VDDQ VCC
AT19
VDDQ VCC
AT23
VDDQ VCC
AT27
VDDQ VCC
AT32
VDDQ VCC
AT36
VDDQ VCC
AV37
VDDQ VCC
AW 22
VDDQ VCC
AW 25
VDDQ VCC
AW 29
VDDQ VCC
AW 33
VDDQ VCC
AY18
VDDQ VCC
BB21
VDDQ VCC
BB22
VDDQ VCC
BB26
VDDQ VCC
BB27
VDDQ VCC
BB30
VDDQ VCC
BB31
VDDQ VCC
BB34
VDDQ VCC
BB36
VDDQ VCC
BD22
VDDQ VCC
BD26
VDDQ VCC
BD30
VDDQ VCC
BD33
VDDQ VCC
BE18
VCORE VDDQ VCC
BE22
VDDQ VCC
BE26
VDDQ VCC
BE30
VDDQ VCC
BE33
VDDQ VCC
VCC
RSVD_AN31 AN31
RSVD VCC
L6
VCC VCC
M6
VCC VCC
AN22
RSVD_AN22
RSVD VCC
RSVD_AN18 AN18
RSVD VCC
VCC
C50
8 VCC_SENSE_R
VCC_SENSE VCC
RSVD_AH9 AH9
RSVD VCC
0_06 0_06 D51
VCCIO_OUT VCC
*0_06 *0_06 F17
FC_F17 VCC
AK6
VCOMP_OUT VCC
RSVD_AN33 AN33
RSVD VCC
RSVD_W9 W 9
RSVD VCC
RSVD_J12 J12
RSVD VCC
AR49
RSVD_AR49
RSVD VCC
VCC
H_CPU_SVIDALRT#_R J53
43.2_1%_04 43.2_1%_04
VIDALERT VCC
H_CPU_SVIDCLK J52
VIDSCLK VCC
H_CPU_SVIDDAT J50
VIDSOUT VCC
VCC
B51
VSS VCC
PWR_DEBUG# F19
PW R_DEBUG VCC
E52
VSS VCC
RSVD_V49 V49
RSVD_TP VCC
RSVD_U49 U49
RSVD_TP VCC
AM49
RSVD_AM49
RSVD_TP VCC
RSVD_W49 W 49
RSVD_TP VCC
V50
VSS VCC
AN49
VSS VCC
AJ49
VSS VCC
AG50
VSS VCC
AK49
VSS VCC
AJ50
VSS VCC
AP49
VSS VCC
AB50
VSS VCC
AP50
VSS VCC
AD50
VSS VCC
AM50
VSS VCC
VCC
A36
VCORE VCC VCC
A38
VCC VCC
A39
VCC VCC
A42
VCC VCC
A43
VCC VCC
A45
VCC VCC
A46
VCC VCC
A48
VCC VCC
AA46
VCC
AA47
VCC
AA8
VCC FC_D5
AA9
VCC FC_D3
5 OF 12 5 OF 12
3
2 1
47W->85A
VCORE VCORE
B43
B45 C173 C173 C140 C140 C131 C131 C133 C133 C127 C127 C145 C145 C162 C162 C134 C134 C169 C169
B46
B48
C27
C28
C31
C32
C34
C36
C38
C39
C42
C43
C45 C160 C160 C170 C170 C168 C168 C119 C119 C115 C115 C118 C118 C114 C114 C6 C6 C10 C10
C46
C48
D27
D28
D31
D32
D34
D36
D38
D39
D42
D43
D45 C136 C136 C137 C137 C158 C158 C161 C161 C157 C157 C163 C163 C164 C164 C116 C116 C139 C139
D46
D48
E27
E28
E31
E32
E34
E36
E38
E39
E42
E43
E45 C124 C124 C117 C117 C8 C8 C120 C120 C121 C121 C149 C149 C7 C7 C4 C4 C1 C1
E46
E48
F27
F28
F31
F32
F34
F36
F38
F39
F42
F43
F45 C154 C154 C132 C132 C128 C128 C153 C153
F46
F48
G27
G29
G31
G32
G34
G36
G38
G39
G42
G43
G45 RESERVE THIS CIRCUIT FOR FUTURE COMPATIBILITY
G46
G48
H11 1.05VS
H12
H13 CPU_FC_PWR R11 R11 *0_08 *0_08
H14
H16
H17
C2 C2
H18
H19
H20
H21
H23
H24
H25
H26
H27
H29
PM_PCH_PWROK 18
D5
CPU_FC_PWR R20 R20
D3 CPU_FC_PWROK *2K_04 *2K_04
CPU_FC_PWROK
R10 R10
*1K_04 *1K_04
! ! ! !!DMFWP!DP/ ! ! ! !!DMFWP!DP/ ! ! ! !!DMFWP!DP/
VDDQ 4,5,10,11,31,34
V_VCCDDQ 31
Title Title Title
VCORE 8,9,35 [07] Processor 5/7-POWER [07] Processor 5/7-POWER [07] Processor 5/7-POWER
VCCIO_OUT 4,35
VCCIO2PCH 24
Size Size Size Document Number Document Number Document Number
VCCIOA_OUT 3,6
6-71-W7400-D03 6-71-W7400-D03 6-71-W7400-D03
Custom Custom Custom SCHEMATIC1 SCHEMATIC1 SCHEMATIC1
1.05VS 4,23,24,32,35
Date: Date: Date: Wednesday, April 24, 2013 Wednesday, April 24, 2013 Wednesday, April 24, 2013 Sheet Sheet Sheet 7 7 7 of of of
2 1
D
C141 C141
C9 C9
C122 C122
C
C148 C148
B
C5 C5
A
Rev Rev Rev
2.0A 2.0A 2.0A
43 43 43