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Schematic Diagrams
Processor 7/7- RSVD
D
PCI EXPRESS STATIC LANE REVERSAL FOR ALL PEG PORTS
CFG2
Sheet 9 of 42
DISPLAY PORT PRESENCE STRAP
Processor 7/7-
RSVD
C
CFG4
PCIE PORT BIFURCATION STRAPS
CFG[6:5]
B
DEFENSIVE PULL DOWN SITE
CFG7
A
B - 10 Processor 7/7- RSVD
5
4
Haswell Processor 7/7 ( RESERVED )
CFG STRAPS FOR PROCESSOR
1: (DEFAULT)NORMAL OPERATION;
LANE# DEFINITION MATCHES
SOCKET PIN MAP DEFINITION
0: LANE REVERSAL
VCORE
CFG2
R243
R243
*1K_04
*1K_04
1: DISABLED;
NO PHYSICAL DISPLAY PORT ATTACHED
TO EMBEDDED DISPLAY PORT
0: ENABLED;
AN EXTERNAL DISPLAY PORT DEVICE
R571
R571
IS CONNECTED TO THE EMBEDDED
*1K_04
*1K_04
DISPLAY PORT
D01A add
CFG4
R238
R238
1K_04
1K_04
11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
CFG5
R242
R242
*1K_04
*1K_04
CFG6
R226
R226
*1K_04
*1K_04
1: (Default) PEG Train immediately following xxRESETB de assertion
0: PEG Wait for BIOS for training
CFG7
R233
R233
*1K_04
*1K_04
5
4
3
HASWELL_BGA_E
HASWELL_BGA_E
U1K
U1K
F1
RSVD_F1
RSVD_TP
E1
RSVD_E1
RSVD_TP
RSVD_BE4
BE4
A5
RSVD_A5
RSVD_TP
RSVD_TP
RSVD_BD3
BD3
A6
RSVD_A6
RSVD_TP
RSVD_TP
RSVD_F6
F6
R54
CFG_RCOMP
RSVD_TP
CFG_RCOMP
RSVD_A35
G6
Y52
CFG16
RSVD_TP
CFG16
V53
CFG17
CFG18
RSVD_G21
G21
Y51
CFG18
RSVD_TP
CFG17
RSVD_G24
G24
V52
CFG19
RSVD_TP
CFG19
TESTLO_F21
F21
TESTLO_F21
G19
B50
RSVD_B50
VSS
RSVD
F51
AH49
RSVD_AH49
VSS
RSVD
F52
AM48
RSVD_AM48
VSS
RSVD
F22
AU27
RSVD_AU27
VCC
RSVD
AU26
RSVD_AU26
RSVD
RSVD_L52
L52
BD4
RSVD_BD4
RSVD_TP
RSVD
RSVD_L53
L53
BC4
RSVD_BC4
RSVD_TP
RSVD
AL6
RSVD_AL6
RSVD
RSVD_L51
L51
F8
RSVD_F8
RSVD_TP
RSVD
RSVD_F24
F24
RSVD_TP
F25
RSVD_F25
RSVD_TP
TESTLO_F20
F20
TESTLO_F20
CFG0
AG49
F16
RSVD_F16
CFG0
RSVD
CFG1
AD49
CFG1
CFG2
AC49
CFG2
CFG3
AE49
CFG3
Y50
CFG4
CFG4
CFG5
AB49
CFG5
CFG6
V51
G12
RSVD_G12
CFG6
RSVD_TP
CFG7
W51
G10
RSVD_G10
CFG7
RSVD_TP
Y49
CFG8
CFG8
CFG9
Y54
H54
CFG9
VSS
CFG10
Y53
H53
CFG10
VSS
CFG11
W53
CFG11
CFG12
U53
H51
CFG12
VSS
CFG13
V54
H52
CFG13
VSS
CFG14
R53
CFG14
R52
N51
CFG15
RSVD_N51
CFG15
RSVD
G53
RSVD_G53
RSVD
RSVD_L50
L50
H50
RSVD_H50
RSVD
RSVD
RSVD_L49
L49
RSVD
E5
RSVD_E5
RSVD
11 OF 12
11 OF 12
TESTLO_F20
R213
R213
49.9_1%_04
49.9_1%_04
TESTLO_F21
R212
R212
49.9_1%_04
49.9_1%_04
CFG_RCOMP
R39
R39
49.9_1%_04
49.9_1%_04
3
2
1
HASWELL_BGA_E
HASWELL_BGA_E
U1L
U1L
TP_A3
A3
DAISY_CHAIN_NCTF_A3
TP_A4
A4
DAISY_CHAIN_NCTF_A4
BF51
TP_BF51
DAISY_CHAIN_NCTF_BF51
BF52
TP_BF52
DAISY_CHAIN_NCTF_BF52
TP_A51
A51
BF53
TP_BF53
DAISY_CHAIN_NCTF_A51
DAISY_CHAIN_NCTF_BF53
TP_A52
A52
DAISY_CHAIN_NCTF_A52
TP_A53
A53
C1
TP_C1
DAISY_CHAIN_NCTF_A53
DAISY_CHAIN_NCTF_C1
C2
TP_C2
DAISY_CHAIN_NCTF_C2
C3
TP_C3
DAISY_CHAIN_NCTF_C3
TP_B2
B2
DAISY_CHAIN_NCTF_B2
TP_B3
B3
C54
DAISY_CHAIN_NCTF_B3
DAISY_CHAIN_NCTF_C54
D1
TP_D1
DAISY_CHAIN_NCTF_D1
TP_B52
B52
DAISY_CHAIN_NCTF_B52
TP_B53
B53
D54
TP_D54
DAISY_CHAIN_NCTF_B53
DAISY_CHAIN_NCTF_D54
B54
TP_B54
DAISY_CHAIN_NCTF_B54
BC1
TP_BC1
DAISY_CHAIN_NCTF_BC1
TP_BC54
BC54
DAISY_CHAIN_NCTF_BC54
TP_BD1
BD1
DAISY_CHAIN_NCTF_BD1
TP_BD54
BD54
DAISY_CHAIN_NCTF_BD54
TP_BE1
BE1
AN35
RSVD_AN35
DAISY_CHAIN_NCTF_BE1
RSVD
BE2
AN37
TP_BE2
RSVD_AN37
DAISY_CHAIN_NCTF_BE2
RSVD
TP_BE3
BE3
AF9
RSVD_AF9
DAISY_CHAIN_NCTF_BE3
RSVD
TP_BE52
BE52
AE9
RSVD_AE9
DAISY_CHAIN_NCTF_BE52
RSVD
TP_BE53
BE53
G14
RSVD_G14
DAISY_CHAIN_NCTF_BE53
RSVD
BE54
G17
TP_BE54
RSVD_G17
DAISY_CHAIN_NCTF_BE54
RSVD
TP_BF2
BF2
AD45
RSVD_AD45
DAISY_CHAIN_NCTF_BF2
RSVD
TP_BF3
BF3
AG45
RSVD_AG45
DAISY_CHAIN_NCTF_BF3
RSVD
TP_BF4
BF4
DAISY_CHAIN_NCTF_BF4
12 OF 12
12 OF 12
! ! ! !!DMFWP!DP/
! ! ! !!DMFWP!DP/
! ! ! !!DMFWP!DP/
Title
Title
Title
[09] Processor 7/7-RSVD
[09] Processor 7/7-RSVD
[09] Processor 7/7-RSVD
Size
Size
Size
Document Number
Document Number
Document Number
Rev
Rev
Rev
6-71-W7400-D03
6-71-W7400-D03
6-71-W7400-D03
7,8,35
VCORE
A3
A3
A3
SCHEMATIC1
SCHEMATIC1
SCHEMATIC1
Date:
Date:
Date:
W ednesday, April 24, 2013
W ednesday, April 24, 2013
W ednesday, April 24, 2013
Sheet
Sheet
Sheet
9
9
9
of
of
of
43
43
43
2
1
D
C
B
A
2.0A
2.0A
2.0A
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