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Processor 2/7- CLK, MISC
5
Haswell Processor 2/7 ( MISC,JTAG,CLK )
D03 del J_XDP1, R572, R573, R574, R575
D
21,30
H_PECI
35
H_PROCHOT#
21
H_THRMTRIP#
18
H_PM_SYNC
21
H_CPUPW RGD
21
PCH_PLTRST_CPU
C
S3 circuit:- DRAM_RST# to memory
should be high during S3
VDDQ
R66
R66
*0_04
*0_04
R68
R68
1K_04
1K_04
BSS138 ( VGS 1.5V )
Q3
Q3
MTN7002ZHS3
MTN7002ZHS3
CPUDRAMRST#
S
D
R67
R67
1K_04
1K_04
R65
R65
DDR3_DRAMRST# 10,11
4.99K_1%_04
4.99K_1%_04
DRAMRST_CNTRL 5,17
C24
C24
0.047u_10V_X7R_04
0.047u_10V_X7R_04
B
Buffered reset to CPU
3.3VS
R43
R43
R37
R37
75_04
75_04
10K_04
10K_04
D
D
R41
R41
43.2_1%_04
43.2_1%_04
2
G
G
2,18,19,27
PLT_RST#
S
S
Q2A
Q2A
D
D
MTDN7002ZHS6R
MTDN7002ZHS6R
5
G
G
S
S
Q2B
Q2B
MTDN7002ZHS6R
MTDN7002ZHS6R
R42
R42
*1.5K_1%_04
*1.5K_1%_04
A
R44
R44
C12
C12
100K_04
100K_04
68P_50V_NPO_04
68P_50V_NPO_04
5
4
3
U1B
U1B
PROC_DETECT#
C51
PROC_DETECT
H_CATERR#
G50
CATERR
G51
R215
R215
*10mil_short
*10mil_short
PECI
H_PROCHOT#
R24
R24
56_1%_04
56_1%_04
E50
PROCHOT
R23
R23
*10mil_short
*10mil_short
D53
THERMTRIP
R22
R22
*100_1%_04
*100_1%_04
1.05VS
R21
R21
*10mil_short
*10mil_short
D52
PM_SYNC
R8
R8
*10mil_short
*10mil_short
H_CPUPW RGD_R
F50
PWRGOOD
PMSYS_PW RGD_BUF
R61
R61
0_04
0_04
AP48
SM_DRAMPWROK
PCH_PLTRST_CPU
R33
R33
0_04
0_04
CPU_RST#
L54
PLTRSTIN
BUF_CPU_RST#
R34
R34
*0_04
*0_04
AC6
R236
R236
0_04
0_04
DPLL_REF_CLKN
22
CLK_DPNS_N
DPLL_REF_CLKN
R231
R231
0_04
0_04
DPLL_REF_CLKP
AE6
22
CLK_DPNS_P
DPLL_REF_CLKP
R228
R228
0_04
0_04
SSC_DPLL_REF_CLKN
V6
22
CLK_DP_N
SSC_DPLL_REF_CLKN
R221
R221
0_04
0_04
SSC_DPLL_REF_CLKP
Y6
22
CLK_DP_P
SSC_DPLL_REF_CLKP
AB6
22
CLK_EXP_N
BCLKN
AA6
22
CLK_EXP_P
BCLKP
S3 circuit:- DRAM PWR GOOD logic
3.3V
3.3V
C13
C13
R52
R52
R56
R56
1
18
PM_DRAM_PW RGD
4
2
U2
U2
*MC74VHC1G08DFT1G
*MC74VHC1G08DFT1G
R45
R45
0_04
0_04
14,31,32,34
SUSB
Q25
Q25
G
30
H_PROCHOT_EC
MTN7002ZHS3
MTN7002ZHS3
R559
R559
1.05VS
100K_04
100K_04
BUF_CPU_RST#
CAD Note: Capacitor need to be placed
close to buffer output pin
R40
R40
*750_1%_04
*750_1%_04
VDD3
2,16,17,18,20,21,22,23,24,26,27,28,30,31,32,33,36
3.3VS
2,6,10,11,13,14,15,16,17,18,19,21,22,23,24,26,27,29,30,31,35
3.3V
3,13,16,21,24,26,31,34
VDDQ
5,7,10,11,31,34
1.05VS
7,23,24,32,35
VCCIO_OUT 7,35
4
3
2
PU/PD for JTAG signals
XDP_TMS
XDP_TDI_R
XDP_PREQ#
XDP_TDO_R
HASWELL_BGA_E
HASWELL_BGA_E
XDP_TCLK
XDP_TRST#
MISC
MISC
BB51
SM_RCOMP_0
XDP_TDO_R
SM_RCOMP0
BB53
SM_RCOMP_1
SM_RCOMP1
BB52
SM_RCOMP_2
SM_RCOMP2
BE51
CPUDRAMRST#
SM_DRAMRST
N53
XDP_PRDY#
PRDY
N52
XDP_PREQ#
XDP_DBR_R
PREQ
N54
XDP_TCLK
TCK
M51
XDP_TMS
TMS
M53
XDP_TRST#
TRST
N49
XDP_TDI_R
DDR3 Compensation Signals
TDI
M49
XDP_TDO_R
TDO
F53
XDP_DBR_R
DBR
R51
XDP_BPM0
SM_RCOMP_0
BPM#0
R50
XDP_BPM1
BPM#1
P49
XDP_BPM2
SM_RCOMP_1
BPM#2
N50
XDP_BPM3
BPM#3
R49
XDP_BPM4
SM_RCOMP_2
BPM#4
P53
XDP_BPM5
BPM#5
U51
XDP_BPM6
BPM#6
P51
XDP_BPM7
BPM#7
2 OF 12
2 OF 12
Processor Pullups/Pull downs
H_PROCHOT#
H_CPUPW RGD_R
VDDQ
TRACE WIDTH 10MIL, LENGTH <500MILS
R57
R57
1.82K_1%_04
1.82K_1%_04
PMSYS_PW RGD_BUF
Supports external Graphics
No integrated graphic and eDP
R53
R53
1.05VS
R60
R60
R49
R49
*39_04
*39_04
R235
R235
*100K_04
*100K_04
R230
R230
Q4
Q4
G
*MTN7002ZHS3
*MTN7002ZHS3
SSC CLOCK TERMINATION STUFF
ONLY WHEN SSC CLOCK NOT USED
VCCIO_OUT
H_PROCHOT#
R220
R220
R227
R227
C422
C422
47P_50V_NPO_04
47P_50V_NPO_04
! ! ! !!DMFWP!DP/
! ! ! !!DMFWP!DP/
! ! ! !!DMFWP!DP/
Title
Title
Title
[04] Processor 2/7-CLK,MISC
[04] Processor 2/7-CLK,MISC
[04] Processor 2/7-CLK,MISC
Size
Size
Size
Document Number
Document Number
Document Number
6-71-W7400-D03
6-71-W7400-D03
6-71-W7400-D03
A3
A3
A3
SCHEMATIC1
SCHEMATIC1
SCHEMATIC1
Date:
Date:
Date:
W ednesday, April 24, 2013
W ednesday, April 24, 2013
W ednesday, April 24, 2013
2
Schematic Diagrams
1
1.05VS
R25
R25
51_04
51_04
R219
R219
51_04
51_04
R35
R35
*51_04
*51_04
R28
R28
51_04
51_04
R36
R36
51_04
51_04
R38
R38
51_04
51_04
R31
R31
*100_04
*100_04
D
3.3VS
1K_04
1K_04
R27
R27
R256
R256
100_1%_04
100_1%_04
R266
R266
75_1%_04
75_1%_04
R265
R265
100_1%_04
100_1%_04
Sheet 4 of 42
VCCIO_OUT
Processor 2/7-CLK,
C
R26
R26
62_04
62_04
MISC
R12
R12
10K_04
10K_04
C11
C11
*0.1u_16V_Y5V_04
*0.1u_16V_Y5V_04
*1K_04
*1K_04
DPLL_REF_CLKN
*1K_04
*1K_04
DPLL_REF_CLKP
B
*10K_04
*10K_04
SSC_DPLL_REF_CLKP
*10K_04
*10K_04
SSC_DPLL_REF_CLKN
A
Rev
Rev
Rev
2.0A
2.0A
2.0A
Sheet
Sheet
Sheet
4
4
4
of
of
of
43
43
43
1
Processor 2/7- CLK, MISC B - 5
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