Table of Contents
Advertisement
Quick Links
LP87524B/J/P-Q1 Technical Reference Manual
This document provides the register bit values for the one-time programmable (OTP) bits of the orderable
part number, LP87524B-Q1, LP87524J-Q1 and LP87524P-Q1.
...................................................................................................................
1
..........................................................................................................................
2
3
Configuration
..................................................................................................................
4
References
1
2
3
4
5
6
LP87524P-Q1 Startup and Shutdown Sequence Timing Diagram
1
Differences between LP87524B/J/P-Q1 devices
2
3
EN, CLKIN and GPIO Pin Settings
4
PGOOD OTP Settings
5
Protections OTP Settings
6
Device Identification and I
7
Interrupt Mask Settings
8
BUCK0, BUCK1, BUCK2, BUCK3 OTP Settings
9
EN, CLKIN and GPIO Pin Settings
10
PGOOD OTP Settings
11
Protections OTP Settings
12
Device Identification and I
13
Interrupt Mask Settings
14
BUCK0, BUCK1, BUCK2, BUCK3 OTP Settings
15
EN, CLKIN and GPIO Pin Settings
16
PGOOD OTP Settings
17
Protections OTP Settings
18
Device Identification and I
19
Interrupt Mask Settings
Trademarks
All trademarks are the property of their respective owners.
SNVU663 - June 2019
Submit Documentation Feedback
.................................................................................................................
.....................................................................................
......................................................................................
.....................................................................................
........................................................................................
......................................................................................................
...................................................................................................
.....................................................................................
2
.....................................................................................................
........................................................................................
.....................................................................................................
.................................................................................................
...................................................................................
2
....................................................................................................
......................................................................................
.....................................................................................................
.................................................................................................
...................................................................................
2
C Settings
....................................................................................................
Copyright © 2019, Texas Instruments Incorporated
Contents
List of Figures
....................................................
...................................................
..................................................
List of Tables
........................................................................
........................................................................
........................................................................
......................................................................
LP87524B/J/P-Q1 Technical Reference Manual
User's Guide
SNVU663 - June 2019
2
2
4
14
2
2
3
8
11
14
4
5
5
6
6
6
7
8
9
10
10
10
10
11
12
13
13
13
13
1
Advertisement
Table of Contents
Subscribe to Our Youtube Channel
Related Manuals for Texas Instruments LP87524B-Q1
Summary of Contents for Texas Instruments LP87524B-Q1
-
Page 1: Table Of Contents
Typical Connection to LP87524B-Q1 ..................Typical Connection to LP87524J-Q1 ..................Typical Connection to LP87524P-Q1 ............ LP87524B-Q1 Startup and Shutdown Sequence Timing Diagram ........... LP87524J-Q1 Startup and Shutdown Sequence Timing Diagram ..........LP87524P-Q1 Startup and Shutdown Sequence Timing Diagram List of Tables ................ -
Page 2: Introduction
1.3 V TPS7A8801 1V0_RF2 2.1 V 1.8 V TPS7D801-Q1 I2C from host Copyright © 2019, Texas Instruments Incorporated Figure 1. Typical Connection to LP87524B-Q1 xWR Radar IC 3.3 V 3.3 V 1.2 V 1.2 V 5.0 V LP87524J-Q1 LC Filter 1V0_RF1 1.0 V... -
Page 3: Typical Connection To Lp87524P-Q1
LC Filter AWR1243 LC Filter LC Filter Copyright © 2019, Texas Instruments Incorporated Figure 3. Typical Connection to LP87524P-Q1 SCL/SDA Pins The SCL and SDA lines (pins 5 & 6, respectively) are used to communicate between the MCU and the LP87524B/J/P-Q1 PMIC using an I C compatible Interface. - Page 4 Input or output in GPIO mode GPIO2_DIR Output Output Output GPIO3_DIR Output Output Output Thermal warning level (125°C or TDIE_WARN_LEVEL 137°C 137°C 125°C 137°C) LP87524B/J/P-Q1 Technical Reference Manual SNVU663 – June 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
- Page 5 EN2 (GPIO2) pin pulldown resistor enable EN2 (GPIO2) pin EN2_PD Disabled or disable EN3 (GPIO3) pin pulldown resistor enable EN3 (GPIO3) pin EN3_PD Disabled or disable SNVU663 – June 2019 LP87524B/J/P-Q1 Technical Reference Manual Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
- Page 6 C and OTP revision ID values. Table 6. Device Identification and I C Settings Description Bit Name LP87524B-Q1 Configurable Slave address 0x60 C slave ID (7-bit) LP87524B/J/P-Q1 Technical Reference Manual SNVU663 – June 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
- Page 7 OTP, in this case with EN1 signal. Refer to the datasheet for a full description of all registers and their settings. SNVU663 – June 2019 LP87524B/J/P-Q1 Technical Reference Manual Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
-
Page 8: Lp87524B-Q1 Startup And Shutdown Sequence Timing Diagram
BUCK2 2 ms BUCK3 1 ms GPIO2 5 ms GPIO3 3 ms Figure 4. LP87524B-Q1 Startup and Shutdown Sequence Timing Diagram 3.1.2 LP87524J-Q1 OTP Configuration Table 8. BUCK0, BUCK1, BUCK2, BUCK3 OTP Settings Description Bit Name LP87524J-Q1 Configurable Buck phase configuration (e.g. four single... - Page 9 Pin control of GPIO, EN1 or EN2 EN_PIN_SELECT_GPIO3 Startup Delay GPIO3_ STARTUP_ DELAY 3 ms Shutdown Delay GPIO3_ SHUTDOWN_ DELAY 0 ms Table 10 shows device settings for PGOOD. SNVU663 – June 2019 LP87524B/J/P-Q1 Technical Reference Manual Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
- Page 10 OTP, in this case with EN1 signal. Refer to the datasheet for a full description of all registers and their settings. LP87524B/J/P-Q1 Technical Reference Manual SNVU663 – June 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
-
Page 11: Lp87524J-Q1 Startup And Shutdown Sequence Timing Diagram
Force PWM BUCK1 Peak current limit ILIM1 2.5 A Slew rate SLEW_RATE1 3.8 mV/µs Startup Delay BUCK1_STARTUP_DELAY 2.24 ms Shutdown Delay BUCK1_SHUTDOWN_DELAY 0.32 ms SNVU663 – June 2019 LP87524B/J/P-Q1 Technical Reference Manual Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated... - Page 12 Pin control of GPIO, EN1 or EN2 EN_PIN_SELECT_GPIO3 Startup Delay GPIO3_ STARTUP_ DELAY 4.16 ms Shutdown Delay GPIO3_ SHUTDOWN_ DELAY 0 ms Table 16 shows device settings for PGOOD. LP87524B/J/P-Q1 Technical Reference Manual SNVU663 – June 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
-
Page 13: Settings
BUCK2 Buck2 current limit triggered BUCK2_ILIM_MASK Masked Buck3 PGOOD has reached threshold BUCK3_PG_MASK Masked level BUCK3 Buck3 current limit triggered BUCK3_ILIM_MASK Masked SNVU663 – June 2019 LP87524B/J/P-Q1 Technical Reference Manual Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated... - Page 14 LP87524B/J/P-Q1 Four 4-MHz Buck Converters for AWR and IWR MMICs datasheet 2. Texas Instruments, XWR1xxx Power Management Optimizations – Low Cost LC Filter Solution application report LP87524B/J/P-Q1 Technical Reference Manual SNVU663 – June 2019 Submit Documentation Feedback Copyright © 2019, Texas Instruments Incorporated...
- Page 15 TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2019, Texas Instruments Incorporated...
Need help?
Do you have a question about the LP87524B-Q1 and is the answer not in the manual?
Questions and answers