onsemi EVBUM2817/D User Manual

Isolated Dual Channel Gate Driver
Evaluation Board User's Manual
EVBUM2817/D
Introduction
This user guide supports the evaluation board for the NCP5156x. It
should be used in conjunction with the NCP5156x and NCV5156x
datasheets as well as onsemi's application notes and technical support
team. Please visit onsemi's website at www.onsemi.com.
This document describes the proposed solution for 5 kV
isolated dual channel gate driver using the NCP51561. This user's
guide also includes information regarding operating procedures,
input/output connections, an electrical schematic, printed circuit board
(PCB) layout, and a bill of material (BOM) for each evaluation board.
These evaluation boards can be used to evaluate:
•
NCP51561xyDWR2G
•
NCV51561xyDWR2G
•
NCP51560xyDWR2G
•
NCP51563xyDWR2G
•
NCV51563xyDWR2G
Description
The NCP5156x are isolated dual−channel gate drivers
with 4.5−A/9−A source and sink peak current respectively. They are
designed for fast switching to drive power MOSFETs, and SiC
MOSFET power switches. The NCP5156x offers short and matched
propagation delays.
Two independent and 5 kV
input to each output and internal functional isolation between the two
output drivers allows a working voltage of up to 1500 VDC. This
driver can be used in any possible configurations of two low side, two
high−side switches or a half−bridge driver with programmable dead
time. An ENA/DIS pin enable or disable both outputs simultaneously
when set high or low for ENABLE or DISABLE mode respectively.
The NCP5156x offer other important protection functions such as
independent under−voltage lockout for both gate drivers and a Dead
Time adjustment function.
Key Features
•
Flexible: Dual Low−Side, Dual High−Side or Half−Bridge Gate
Driver
•
Independent UVLO Protections for Both Output Drivers
•
Output Supply Voltage from 6.5 V to 30 V with 5−V, 8−V for
MOSFET, 13−V and 17−V UVLO for SiC, Thresholds
•
4.5−A Peak Source, 9−A Peak Sink Output
•
Common Mode Transient Immunity CMTI >200 V/ns
•
Propagation Delay Typical 36 ns with
♦
5 ns Max Delay Matching per Channel
♦
5 ns Max Pulse−Width Distortion
•
User Programmable Input Logic
♦
Single or Dual−Input Modes Via ANB (NCP51561/563 only)
♦
ENABLE or DISASBLE Mode
© Semiconductor Components Industries, LLC, 2021
November, 2021 − Rev. 1
internal galvanic isolation from
RMS
EVAL BOARD USER'S MANUAL
RMS
Figure 1. Evaluation Board Picture
FUNCTIONAL BLOCK DIAGRAM
V
DD
VDD UVLO
INA
INA
INB
INB
ANB
VDD
ENA/DIS
DT
GND
1
www.onsemi.com
Type−A
Type−B
Type−C
PIN CONNECTIONS
INA VCCA 16
INB OUTA 15
VSSA
V 14
DD
NC 13
GND
ENA/DIS NC
12
DT VCCB
11
ANB OUTB
10
V VSSB
9
DD
UVLO
[5V, 8V, 17V]
INA
Tx Rx
LOGIC
LOGIC
Functional
Isolation
UVLO
[5V, 8V, 17V]
INB
DEAD Tx Rx
LOGIC
TIME
CONTROL
Publication Order Number:
EVBUM2817/D
VCCA
OUTA
VSSA
NC
NC
VCCB
OUTB
VSSB