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6-6) Input Signal Timing Chart
6-6-1 Data update mode (1 line)
Updates data of only one specified line. (M0="Hi"、M2＝"Lo")
SCS
SI
M0
M1
M2 DMY DMY DMY DMY
SCLK
Mode selection period
( 3ck+5ckDMY )
M0 : Mode flag.
Set for "Hi". Data update mode (Memory internal data update)
When "Lo", display mode (maintain memory internal data).
M1 : Frame inversion flag.
When "Hi", outputs VCOM="Hi", and when "Lo", outputs VCOM="Lo".
When EXTMODE="Hi", it can be "Hi" or "Lo".
M2 : All clear flag.
Refer to (6-6-4) All Clear Mode to execute clear.
DUMMY Data : Dummy data.：It can be "Hi" or "Lo" ("Lo" is recommended.)
D0 – D143 ：Writing Image data ( Horizontal Line data )
※ Data write period
Data is being stored in 1
※ Data transfer period
Data written in 1
※For gate line address setting, refer to 6-7) Input Signal and Display.
※M1: Frame inversion flag is enabled when EXTMODE="Lo".
※When SCS becomes "Lo", M0 and M2 are cleared.
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SPEC No.
DMY
AG0 AG1 AG2 AG3 AG4 AG5 AG6
Gateline address period
( 8clk )
Figure 6-6-1 Data update mode by 1line
Hi ： White
Lo ： Black
st
latch block of binary driver on panel.
st
latch is being transferred (written) to pixel internal memory circuit.
MODEL No.
LD-29608A
LS013B7DH01
AG7
D0
D1
D2
D141
Data writing period
( 144clk )
DMY (don't care)
D142
D143
Data transfer period
( 16clk )
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