Analog Devices EVAL-AD7723CB Quick Start Manual page 2

EVAL-AD7723CB
Link and Switch Options
There are 37 link options which must be set for the required operating setup before using the evaluation board. The
functions of these options are outlined below.
Link No. Function.
J1 J2 Both of these links must be used together. These links are in place when using an AIN signal that is biased
around 0V. These links are removed when using an AIN signal that is biased around 2.5V. The
noise floor of high quality signal sources will, in most cases, be higher than the actual noise floor
of the AD7723. For this reason, it is important that the signal source should be filtered using a bandpass
or, for low frequency signals, a lowpass filter before being applied to the signal input of the evaluation
board. For low frequency signal sources, a simple RC lowpass filter is sufficient to demonstrate the very
low noise floor of the AD7723.
J 3 This link selects the clock source for the AD7723. In position "B" the on-board CMOS clock oscillator
is selected. In position "A" an external sampling clock connected to SK2 is selected. To use the AD7723's
crystal oscillator circuit, J3 must be removed and a 19.6MHz quartz crystal must be inserted in position
Y1, two 33pF ceramic (0603 case) capacitors must be inserted in positions C13 & C14 and a 1M
resistor (0805 case) must be inserted in position R12.
J 4 This link is used to select the source of the AV
supplied from the external power terminal P2. In position "B" the AV
EVAL-CONTROL BOARD.
J 5 This link is used to choose the power source for the positive supply pin of the op-amps (V+). When
connecting to the EVAL-CONTROL BOARD, this link must be removed if using the AD8047 op-amps
supplied with the evaluation board. In this case, an external +7.5V must be supplied via the "+VS" pin
of P2. If using AD8041 op-amps (not supplied), this link can remain in place and the EVAL-CONTROL
BOARD can supply the required +5V. Please note that using AD8041 op-amps causes a 2dB degradation
in the ADC's SNR.
J 6 This link is used to choose the power source for the negative supply pin of the op-amps (V-). When
connecting to the EVAL-CONTROL BOARD, this link must be removed if using the AD8047 op-amps
supplied with the evaluation board. In this case, an external -2.5V must be supplied via the "-VS" pin
of P2. If using AD8041 op-amps (not supplied), this link can remain in place and the EVAL-CONTROL
BOARD supplies -5V. Although the EVAL-CONTROL BOARD supplies a dual 5V power supply to
the AD7723 evaluation board, the AD8041 only requires a single 5V power supply when being used with
the AD7723. Please note that using AD8041 op-amps causes a 2dB degradation in the ADC's SNR.
J7 J8 J9 J10 These jumpers allow operation with either the internal reference of the AD7723 or the AD780 external
reference. To operate the board using the internal reference of the AD7723, both links, J9 & J10 must
be removed and both links, J7 & J8 must be in position "A". To operate the board using the external
reference (AD780), both links, J9 & J10 must be in place, link J7 must be in position "B" and remove
link J8.
J11 This link selects the reference voltage output from the AD780 voltage reference. When this link is "in
place" the AD780 produces a +3V reference. When this link is "removed" the AD780 produces a +2.5V
reference.
J12 J13 These links are used to select serial mode or parallel mode operation. J12 corresponds to MODE1 while
J13 corresponds to MODE2. With a link in position "A", the corresponding MODE pin is tied to AV
while the pin is tied to GND when its corresponding link is in position "B". With both of these links in
position "B" the AD7723 is configured for serial operation. Any other combination of these links
selects parallel mode operation, the polarity of the MODE pins determining whether decimate by 16
mode, decimate by 32 mode (lowpass) or bandpass mode is selected. See Table 1 and Table 2 on the
AD7723 Data Sheet for further information. Note that the AD7723 can only be used in decimate by
32 mode when interfaced to the EVAL-CONTROL BOARD and running on a 19.2 MHz clock. To
interface the AD7723 to the EVAL-CONTROL BOARD in decimate by 16 mode, the master clock
must be reduced to less than 16 MHz.
J14 J15 These two links are used together in parallel mode operation to select how the conversion data is latched
into the 16-bit data register (U7). With the header shunt installed in J15, conversion results are latched
on the falling edge of the
latched on the rising edge of the
J16 J17 In serial mode operation, J16 must be removed and J17 must be in position "B". In parallel mode
operation, J16 is inserted and J17 is removed.
power plane. In position "A" the AV
DD
output. With the header shunt installed in J14, conversion results are
output.
– 2 –
power plane is
DD
power plane is supplied by the
DD
DD
REV. B