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4.5.4
INTERRUPT SELECT REGISTER
North Star HSIO-4
Each port has a three-bit Interrupt Select
Register. Physically, each bit is in a
different IC (Locations 5F, 5E, 5D).
Logically, the Interrupt Select Register is a
single register loaded from the three least
significant data bits of an output instruction
from the processor. Each bit in the register
controls the arming/disarming of one flag from
the USART. Only if a flag is armed is it ORed
into the interrupt signal for the I/O port.
Bit 0 arms the TRANSMIT EMPTY SIGNAL
Bit 1 arms the TRANSMIT READY SIGNAL
Bit 2 arms the RECEIVE READY SIGNAL
The Synchronous Detect Flag, which is armed by
a mini-jump, is only used for synchronous
transmission.
63
User/Technical Manual
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