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Document type:
Title:
User's Manual (MUT)
Mod. V977 16 Channel I/O Register (Status A)
4.12. Singlehit read-clear register
(Base address + %0016 read only)
Each register's bit corresponds to one channel. This is a different way to access the
SINGLE HIT READ REGISTER: a read access to this register clears the first FLIP -FLOP
(see § 3.1) of all channels.
15 14 13 12 11 10 9
4.13. Multihit read-clear register
(Base address + %0018 read only)
Each register's bit corresponds to one channel. This is a different way to access the
MULTI HIT READ REGISTER: a read access to this register clears the second FLIP-
FLOP (see § 3.1) of all channels.
15 14 13 12 11 10 9
4.14. Test control register
(Base address + %001A read/write)
This register handles all the TEST INPUT channel operations.
15 14 13 12 11 10 9
CLEAR BIT: write only. By setting this bit to 1, the TEST CHANNEL FLIP-FLOP is
cleared.
MASK BIT: read/write. If this bit is set to 1, the TEST output is "masked": it does not
produce an output signal (default setting = 0).
OR MASK BIT: read/write. If this bit is set to 1, the Q signal of the TEST channel is not
sent to the OR logic (default setting = 0).
INTERRUPT MASK BIT: read/write. If this bit is set to 1, the Q signal of the TEST
channel is not sent to the INTERRUPT logic (default setting = 0).
READ BIT: read only. It reproduces the pushbutton status, regardless the MASK bit
status.
NPO:
00118/01:V977X.MUTX/01
8
7
6
5
4
3
2
SINGLEHIT READ-CLEAR
8
7
6
5
4
3
2
MULTIHIT READ-CLEAR
8 7
6
5 4
3
2
Filename:
V977_REV1.DOC
Revision date:
27/08/2004
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TEST CH CLEAR
TEST CH MASK
TEST CH OR MASK
TEST CH INTERRUPT MASK
TEST CH READ
Revision:
1
Number of pages:
Page:
21
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