Output Set Register; Output Mask Register; Interrupt Mask; Output Clear Register - Caen V977 Technical Information Manual

Document type: Title:
User's Manual (MUT) Mod. V977 16 Channel I/O Register (Status A)

4.8. Output set register

(Base address + %000A read/write)
Each register's bit corresponds to one channel. If one bit is set to 1, the corresponding
channel output is active, regardless the corresponding input connector's and FLIP-
FLOPs' Qs status.
15 14 13 12 11 10 9
This register default content is 0x0000.

4.9. Output mask register

(Base address + %000C read/write)
Each register's bit corresponds to one channel. If one bit is set to 1, the relevant output is
"masked" and no output signal is produced regardless the FLIP FLOPs status. The output
signal can be produced anyway via the relevant bit in the OUTPUT SET register (see §
4.8).
15 14 13 12 11 10 9
This register default content is 0x0000: all channels outputs are enabled.

4.10. Interrupt mask

(Base address + %000E read/write)
Each register's bit corresponds to one channel, and it is "masked" as the corresponding
bit is set to 1. The interrupt request (whose level is set by the INTERRUPT LEVEL
register value) is produced when the OR of the channels non mascherati has a TRUE
status.
15 14 13 12 11 10 9
This register default content is 0x0000: all channels are unmasked.

4.11. Output clear register

(Base address + %0010 read/write)
A dummy write access to this register clears all the channels FLIP-FLOP.
NPO:
00118/01:V977X.MUTX/01
8 7 6 5 4 3
OUTPUT SET
8 7 6 5 4 3
OUTPUT MASK
8 7 6 5 4 3
INTERRUPT MASK
Filename:
V977_REV1.DOC
Revision date:
27/08/2004
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Revision:
1
Number of pages: Page:
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