Table of Contents
Advertisement
Document type:
Title:
User's Manual (MUT)
Mod. V977 16 Channel I/O Register (Status A)
3.1.1. I/O register mode
The module operates as I/O register if the PATTERN bit of the CONTROL REGISTER is
set to 0 (default setting).
In this case the simplified channel scheme is shown in Fig. 3.2.
PATTERN = 0
INPUT MASK
VME REGISTER
CH #n
INPUT
INPUT READ
VME REGISTER
GATE
INPUT
CONTROL
REGISTER
GATE MASK BIT
In this operating mode the output of one channel is active when a single hit (from front
panel or VME generated) is received. The output can also be set by a write access to the
OUTPUT SET REGISTER.
The outputs can also be masked, individually for each channel, through the OUTPUT
MASK REGISTER.
In this operating mode, the two channel LEDs identify the channel status in the following
way:
Left LED: input signal active;
Right LED: output signal active.
3.1.2. Multihit pattern unit mode
The module operates as multihit pattern unit if the PATTERN bit of the CONTROL
REGISTER is set to 1.
In this case the simplified channel scheme is shown in Fig 3.3.
NPO:
00118/01:V977X.MUTX/01
1
D
Q
AR
INPUT SET
VME REGISTER
AR
CLEAR
CLEAR OUTPUT
INPUT
VME REGISTER
Fig. 3.2: I/O register mode
Filename:
V977_REV1.DOC
Revision date:
27/08/2004
OUTPUT MASK
VME REGISTER
SINGLE HIT READ
VME REGISTER
to OR and IRQ
LOGIC
Revision:
1
OUTPUT SET
VME REGISTER
CH #n
OUTPUT
Number of pages:
Page:
21
10
Advertisement
Table of Contents
