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Technical Information Manual Revision n. 1 27 August 2004 MOD. V977 16 CHANNEL I/O Register (Status A) MANUAL REV.1 NPO: 00118/01:V977X.MUTX/01...
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User. It is strongly recommended to read thoroughly the CAEN User's Manual before any kind of operation. CAEN reserves the right to change partially or entirely the contents of this Manual at any time and without giving any notice.
1. Overview 1.1. Module description The Mod. V977 is a 1-unit wide VME module that can work either as 16 channel general purpose I/O Register or as Multihit Pattern Unit; the operating mode is selected via VME and is signalled via front panel LED.
Mod. V977 16 Channel I/O Register (Status A) 27/08/2004 3. Operating modes 3.1. Functional description The Mod. V977 is a 16 channel general purpose I/O Register or as Multihit Pattern Unit The following figure shows the simplified scheme of a single channel: CONTROL REGISTER...
Title: Revision date: Revision: User's Manual (MUT) Mod. V977 16 Channel I/O Register (Status A) 27/08/2004 3.1.1. I/O register mode The module operates as I/O register if the PATTERN bit of the CONTROL REGISTER is set to 0 (default setting).
Also the TEST signal participates to the OR logic (it can also be masked). 3.3. Interrupter capability The Mod. V977 house a VME INTERRUPTER. The module responds to D16 Interrupt Acknowledge cycles providing a word whose 8 LSB are the STATUS/ID.
Document type: Title: Revision date: Revision: User's Manual (MUT) Mod. V977 16 Channel I/O Register (Status A) 27/08/2004 4. VME Interface 4.1. Addressing capability The module works in A32/A24 mode. This means that the module address must be specified in a field of 32 or 24 bits. The Address Modifiers code recognized by the module...
Base address bit <31~28> selection (SW2) Fig. 4.1: Mod. V977 Base address setting and output selection 4.3. Input set register (Base address + %0000 read/write) Each register’s bit corresponds to one channel. If one bit is set to 1 the relevant channel FLIP -FLOP (see §...
Title: Revision date: Revision: User's Manual (MUT) Mod. V977 16 Channel I/O Register (Status A) 27/08/2004 4.4. Input mask register (Base address + %0002 read/write) Each register’s bit corresponds to one channel. If one bit is set to 1 , the related input signal is “masked”;...
Title: Revision date: Revision: User's Manual (MUT) Mod. V977 16 Channel I/O Register (Status A) 27/08/2004 4.8. Output set register (Base address + %000A read/write) Each register’s bit corresponds to one channel. If one bit is set to 1, the corresponding channel output is active, regardless the corresponding input connector’s and FLIP-...
Title: Revision date: Revision: User's Manual (MUT) Mod. V977 16 Channel I/O Register (Status A) 27/08/2004 4.12. Singlehit read-clear register (Base address + %0016 read only) Each register’s bit corresponds to one channel. This is a different way to access the SINGLE HIT READ REGISTER: a read access to this register clears the first FLIP -FLOP (see §...
4.16. Interrupt vector (Base address + %0022 read/write ) This register contains the STATUS-ID that the V977 places on the VME data bus during the interrupt -acknowledge cycle (Bits 8 to 15 are meaningless ). 15 14 13 12 11 10 9...