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Document type:
Title:
User's Manual (MUT)
Mod. V977 16 Channel I/O Register (Status A)
4.4. Input mask register
(Base address + %0002 read/write)
Each register's bit corresponds to one channel. If one bit is set to 1 , the related input
signal is "masked"; i.e. if a channel is masked the relevant FLIP -FLOP does not receive
the front panel signal. The FLIP -FLOPs' Qs can be activated anyway via the relevant bit
in the INPUT SET register (see § 4.3).
15 14 13 12 11 10 9
This register default content is 0x0000: all channels inputs are enabled.
4.5. Input read register
(Base address + %0004 read only)
Each register's bit corresponds to one channel: it reproduces the relevant input
connector's logic level, regardless the INPUT MASK register's status.
15 14 13 12 11 10 9
4.6. Single-hit read register
(Base address + %0006 read only)
Each register's bit corresponds to one channel: it reproduces the relevant FLIP-FLOPs'
Qs, regardless the OUTPUT MASK register's status. Each bit is set to one as the
corresponding channel as received one hit (from front panel or VME generated).
15 14 13 12 11 10 9
SINGLEHIT READ
4.7. Multi-hit read register
(Base address + %0008 read only)
Each register's bit corresponds to one channel. Each bit reproduces the relevant FLIP-
FLOPs' Qs, regardless the OUTPUT MASK register's status. This register is used only if
the module operates in multihit pattern unit mode and signals if one channel has received
a double input hit (from front panel or VME generated).
15 14 13 12 11 10 9
MULTIHIT READ
NPO:
00118/01:V977X.MUTX/01
8
7 6
5 4 3
INPUT MASK
8
7 6
5 4 3
INPUT READ
8
7 6
5 4 3
8 7
6
5 4 3
Filename:
V977_REV1.DOC
Revision date:
27/08/2004
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1 0
2
1 0
2
1 0
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1 0
Revision:
1
Number of pages:
Page:
21
16
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