EEMEM PROTECTION
The write protect ( WP ) pin disables any changes to the
scratchpad register contents, except for the EEMEM setting,
which can still be restored using Instruction 1, Instruction 8,
and the PR pulse. Therefore, WP can be used to provide a
hardware EEMEM protection feature. To disable WP , it is
recommended to execute a NOP instruction before returning
WP to logic high.
DIGITAL INPUT/OUTPUT CONFIGURATION
All digital inputs are ESD protected, high input impedance that
can be driven directly from most digital sources. Active at logic
low, PR and WP must be tied to V
internal pull-up resistors are present on any digital input pins.
To avoid floating digital pins that might cause false triggering in
a noisy environment, pull-up resistors should be added. This is
applicable when the device is detached from the driving source
once it is programmed.
The SDO and RDY pins are open-drain digital outputs that
need pull-up resistors only if these functions are used. To
optimize the speed and power trade-off, use 2.2 kΩ pull-up
resistors.
The equivalent serial data input and output logic is shown in
Figure 36. The open-drain output SDO is disabled whenever
chip-select CS is in logic high. ESD protection of the digital
inputs is shown in Figure 37 and Figure 38.
VALID
COMMAND
COUNTER
CLK
REGISTER
CS
SDI
Figure 36. Equivalent Digital Input-Output Logic
LOGIC
PINS
Figure 37. Equivalent ESD Digital Input Protection
, if they are not used. No
DD
PR
WP
COMMAND
5V
PROCESSOR
AND ADDRESS
DECODE
R
PULL-UP
SERIAL
(FOR DAISY
CHAIN ONLY)
SDO
GND
AD5235
V
DD
INPUTS
300 Ω
GND
WP
SERIAL DATA INTERFACE
The AD5235 contains a 4-wire SPI compatible digital interface
(SDI, SDO, CS , and CLK). The 24-bit serial data-word must be
loaded with MSB first. The format of the word is shown in
Table 6. The command bits (C0 to C3) control the operation of
the digital potentiometer according to the command shown in
Table 7. A0 to A3 are the address bits. A0 is used to address
RDAC1 or RDAC2. Addresses 2 to 14 are accessible by users for
extra EEMEM. Address 15 is reserved for factory usage. Table 9
provides an address map of the EEMEM locations. The data bits
(D0 to D9) are the values for the RDAC registers. The data bits
(D0 to D15) are the values for the EEMEM registers.
The AD5235 has an internal counter that counts a multiple of
24 bits (a frame) for proper operation. For example, AD5235
works with a 24-bit or 48-bit word, but it cannot work properly
with a 23-bit or 25-bit word. In addition, AD5235 has a subtle
feature that, if CS is pulsed without CLK and SDI, the part
repeats the previous command (except during power-up). As a
result, care must be taken to ensure that no excessive noise
exists in the CLK or CS line that might alter the effective
number-of-bits pattern. Also, to prevent data from mislocking
(due to noise, for example), the counter resets, if the count is not
a multiple of four when CS goes high.
The SPI interface can be used in two slave modes: CPHA = 1,
CPOL = 1 and CPHA = 0, CPOL = 0. CPHA and CPOL refer to
the control bits that dictate SPI timing in the following
MicroConverters and microprocessors: ADuC812/ADuC824,
M68HC11, and MC68HC16R1/MC68HC 916R1.
DAISY-CHAIN OPERATION
The serial data output pin (SDO) serves two purposes. It can be
used to read the contents of the wiper setting and EEMEM
values using Instructions 10 and 9, respectively. The remaining
instructions (0 to 8, 11 to 15) are valid for daisy-chaining
multiple devices in simultaneous operations. Daisy-chaining
minimizes the number of port pins required from the
controlling IC (Figure 39). The SDO pin contains an open-drain
N-Ch FET that requires a pull-up resistor, if this function is
used. As shown in Figure 39, users need to tie the SDO pin of
one package to the SDI pin of the next package. Users might
need to increase the clock period, because the pull-up resistor
Rev. B | Page 15 of 28
V
DD
INPUT
300 Ω
GND
Figure 38. Equivalent WP Input Protection
AD5235
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