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A S P M E T E R C O M M I S S I O N I N G
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ASPMETER commissioning
Configuring alarm registers
Latching alarms
Once the alarm threshold is crossed into an alarm state and
after the associated alarm timer expires, the corresponding
latching status bit is set and is not reset until the status bit
is manually cleared by writing the alarm status register or
resetting latching alarms, even if the signal is no longer in
an alarm state. The alarm is also cleared if the threshold
is changed.
Non-latching alarms
Once the alarm threshold is crossed into an alarm state, the
corresponding non-latching status bit is set. The non-latching
status bit is cleared once the signal crosses the threshold
(plus hysteresis) out of an alarm state.
Alarm timers
These timers control entry into an alarm state. All channels
use the same global per-panel timers; per-panel timers only
apply to latching alarms.
Registers 165–170:
• High-high latching alarm time delay
• High latching alarm time delay
• Low latching alarm time delay
• Low-low latching alarm time delay
• Latching alarm ON time (when current is above low-low
alarm, then ON state is declared)
• Latching alarm OFF state (current is below low-low alarm
and ON state was declared)
Alarm thresholds
All values are expressed as a percentage of breaker size.
All channels use the same global per-panel values. An entry
of 0% will disable the alarm for that channel. Hysteresis only
applies to non-latching alarms.
Registers 171–177:
• High-high latching alarm threshold
• High alarm latching alarm threshold
• Low alarm latching alarm threshold
• Low-low latching alarm threshold
• Non-latching high threshold
• Non-latching low threshold
• Hysteresis (0–100% percent of setpoint;
non-latching alarms only)
Branch current alarms
Latching alarms are cleared by writing a 0 to its alarm bit.
A write to a non-latching alarm is ignored.
Registers 178–219:
• Bit 0: High-high latching alarm
• Bit 1: High latching alarm
• Bit 2: Low latching alarm
• Bit 3: Low-low latching alarm
• Bit 4: Latching alarm OFF state declared
• Bit 5–7: Reserved for future use (reads 0)
• Bit 8: High non-latching alarm
• Bit 9: Low non-latching alarm
• Bit 10–15: Reserved for future use (reads 0)
AUX current alarms
Latching alarms are cleared by writing a 0 to its alarm bit.
Registers 220–223:
• Bit 0: High-high latching alarm
• Bit 1: High latching alarm
• Bit 2: Low latching alarm
• Bit 3: Low-low latching alarm
• Bit 4: Latching alarm OFF
• Bit 5–7: Reserved for future use (reads 0)
• Bit 8: High non-latching alarm
• Bit 9: Low non-latching alarm
• Bit 10–15: Reserved for future use (reads 0)
Line-to-line voltage alarm timers
These timers control entry into an alarm state. All channels use
the same global per-panel channels. Voltage alarms are global;
settings and alarms are shared between both panels for main
boards with four ribbon cable connections.
Registers 236–237:
• Overvoltage alarm timer
• Undervoltage alarm timer
Line-to-line voltage alarm thresholds
Thresholds are expressed as volts. An entry of 0 disables
that alarm for all channels.
Registers 238–240:
• Overvoltage alarm threshold
• Undervoltage alarm threshold
• Voltage alarm hysteresis
(percentage of setpoint)
37
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