Panasonic PT-43LCX64 Service Manual page 84

VIDEO SIGNAL PATH III BLOCK DIAGRAM (Models: PT-43LCX64 / PT-50LCX65)
LCD DRIVE C.B.A.
IC2503 (LVDS RECEIVER)
LVDS DATA A(+) P2501-14 10
LVDS DATA A(-) P2501-15 9
LVDS DATA B(+) P2501-11 12
LVDS SERIAL TO
LVDS DATA B(-) P2501-12 11
TTL PARALLEL
FROM VIDEO II
LVDS DATA C(+) P2501-8 16
CONVERTER
SIGNAL PATH
LVDS DATA C(-) P2501-9 15
BLOCK DIAGRAM
LVDS DATA D(+) P2501-2
20
LVDS DATA D(-) P2501-3 19
LVDS CLOCK(+) P2501-5 18
LVDS CLOCK(-) P2501-6 17
PLL
IC2502
13,23,31,40,48,56
+3.3V
+5V 5 4 VCC
REG.
<FROM IC2304(52)> RESET(L)
<FROM IC2304(57)> CORRECT ON(L)
IC2505 (SIGNAL PROCESS FOR LCD PANEL)
R DATA (8BIT)
30,32-35, A5-A7,B6-B8,
37-39 C7,C8
NON UNIFORMITY COLOR COMPENSATION
G DATA (8BIT) GAMMA CORRECTION
41-43,45-47, A10-A12,B10-B12,
49,50 C10,C11
WHITE BALANCE CONTROL
TIMING GENERATOR FOR PANEL DRIVE
B DATA (8BIT)
1-3,5,51, A15,A16,B14-B16,
53-55 C14-C16
H-SYNC 29 E2 H-SYNC
V-SYNC 27 D2 V-SYNC
26 E1 CLOCK(76 MHz)
C19 RESET(L)
CORRECT ON(L)
H2
H4,H5,ETC
+3.3V VDD2(+3.3V)
IC2501
D7,D8,ETC
+1.8V
8 1 VDD1(+1.8V)
REG.
IC2001 (SAMPLING HOLD)
R DATA (10BIT)
W4-W6,Y1-Y7 86-95
S/H CLOCK(R) V2 96
CONTROL
XFR(R)
V1 97
LOGIC
STSQO(R) W3 98
& DAC LATCH
FRP U1 99
100
DY M19 24
23
DX Y10 33
ENABLE 4 V9 37
ENABLE 3 W9 36
LEVEL
ENABLE 2 Y9 35
SHIFTER
ENABLE 1
W10 34 (3.3V --> 15.5V)
NRG M1 27
22
CLX W8 38
CLY
M18 25
3
SERIAL
5
INTERFACE
4
V-REF-H(+7V) 12
SCALE
11
CONTROL
V-REF-L(+5V)
10
IC2002 (SAMPLING HOLD)
G DATA (10BIT)
W15-W19,Y16-Y20 86-95
S/H CLOCK(G) W13 96
CONTROL
XFR(G) V13 97
LOGIC
STSQO(G)
Y15 98
& DAC LATCH
XFRP Y13 99
100
24
23
33
37
36
LEVEL
35
SHIFTER
34
(3.3V --> 15.5V)
27
22
38
25
3
SERIAL
5
INTERFACE
4
V-REF-H(+7V) 12
SCALE
11
CONTROL
V-REF-L(+5V) 10
IC2003 (SAMPLING HOLD)
D20,E19,E20,F19,F20, B DATA (10BIT)
G19,G20,H19,H20,J18
86-95
S/H CLOCK(B) K20 96
CONTROL
XFR(B) K18 97
LOGIC
STSQO(B) J19 98
& DAC LATCH
99
100
24
23
33
37
36
LEVEL
35
SHIFTER
34
(3.3V --> 15.5V)
27
22
38
25
3
SERIAL
5
INTERFACE
4
V-REF-H(+7V)
12
SCALE
11
CONTROL
V-REF-L(+5V) 10
XDIR-X <FROM IC2304 (60)>
IC2504 (BUFFER) DIR-X <FROM IC2304 (59)>
DIR-Y <FROM IC2304 (50)>
SERIAL DATA 0 SERIAL DATA 0
B18 2 18
SERIAL CLOCK SERIAL CLOCK
B20 3 17
7 13 IC2001 CS(L)
FROM
SYSTEM CONTROL
IC2002 CS(L) BLOCK DIAGRAM
5 15
4 16 IC2003 CS(L)
CS(L) IC2505CS(L)
B19 6 14
TP2001
6 (IC2001 PIN52 LINE)
TP2004
D/A INVERTER ON/OFF
52,54,56,58,60,62,
CONVERTER AMP SW 64,66,68,70,72,74
VCC(A) 15,26,53,57,61,65,69,73,82 +15.5V
VCC(D) 1,50 +3.3V
19
18
39
43
42
41
40
28
44
45
20
21
81 V-REF-H(+7.5V)
SCALE
80
CONTROL
79 V-REF-L(+7V)
V1
77
V2
78
LCDCOM
D/A CONVERTER AMP SW 13
TP2002
(IC2002 PIN74 LINE)
6
TP2005
D/A
INVERTER ON/OFF 52,54,56,58,60,62,
CONVERTER 64,66,68,70,72,74
AMP SW
VCC(A) 15,26,53,57,61,65,69,73,82 +15.5V
VCC(D) 1,50 +3.3V
19
18
39
43
42
41
40
28
17
44
45
20
21
81 V-REF-H(+7.5V)
SCALE
80
CONTROL
79 V-REF-L(+7V)
V1
77
V2
78
LCDCOM
D/A CONVERTER AMP SW
13
TP2003
(IC2003 PIN52 LINE)
6
TP2006
D/A
INVERTER ON/OFF 52,54,56,58,60,62,
CONVERTER AMP SW 64,66,68,70,72,74
VCC(A) +15.5V
15,26,53,57,61,65,69,73,82
VCC(D) 1,50 +3.3V
19
18
39
43
42
41
40
28
44
45
20
21
81 V-REF-H(+7.5V)
SCALE
80
CONTROL
V-REF-L(+7V)
79
V1
77
V2
78
LCDCOM
D/A CONVERTER AMP SW 13
Q2003
VIDEO SIGNAL(MAIN/SUB)
LCD(R)
+15.5V
P2001-1
P2001-2
P2001-3
P2001-4
P2001-5
P2001-6
P2001-(7-18)
P2001-19
P2001-20
P2001-21
P2001-22
P2001-23
P2001-24
P2001-25
P2001-26
P2001-27
P2001-28
P2001-29
P2001-30
P2001-31
P2001-32
P2001-33
P2001-34
P2001-35
P2001-36
LCD(G)
P2002-1
P2002-2
P2002-3
P2002-4
P2002-5
P2002-6
P2002-36
P2002-(7-18)
P2002-19
P2002-20
P2002-21
P2002-22
P2002-23
P2002-24
P2002-25
P2002-26
P2002-27
P2002-28
P2002-29
P2002-30
P2002-31
P2002-32
P2002-33
P2002-34
P2002-35
P2002-36
LCD(B)
P2003-1
P2003-2
P2003-3
P2003-4
P2003-5
P2003-6
P2003-(7-18)
P2003-19
P2003-20
P2003-21
P2003-22
P2003-23
P2003-24
P2003-25
P2003-26
P2003-27
P2003-28
P2003-29
P2003-30
P2003-31
P2003-32
P2003-33
P2003-34
P2003-35
P2003-36
TP2901
VIDEO SIGNAL PATH III BLOCK DIAGRAM
PT-43LCX64/PT-50LCX64