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Table 30
Item
Address hold time
Address setup time
System cycle time
Data setup time
Data hold time
Access time
Output disable time
Enable HIGH pulse
width
Enable LOW pulse
width
Table 31
Item
Address hold time
Address setup time
System cycle time
Data setup time
Data hold time
Access time
Output disable time
Enable HIGH pulse
width
Enable LOW pulse
width
*1
This is the case of accessing by E when CS1 = LOW.
*2
This is the case of accessing by CS1 when E = HIGH.
*3
The rise and fall times (
time at high speed, they are specified for (
*4
All timings are specified based on the 20 and 80% of V
t
t
*5
and
are specified for the overlap period when CS1 is at LOW (CS2 = HIGH) level and E is at the
EWLW
EWLR
HIGH level.
S1D15710 Series (Rev. 1.1c)
Signal
Symbol
A0
t
t
D0 to D7
t
t
Read
E
t
EWHR
Write
t
EWHW
Read
E
t
EWLR
Write
t
EWLW
Signal
Symbol
A0
t
t
D0 to D7
t
t
Read
E
t
EWHR
Write
t
EWHW
Read
E
t
EWLR
Write
t
EWLW
t
t
and
) of the input signal are specified for less than 15 ns. When using the system cycle
r
f
t
t
+
r
[V
Condition
t
AH6
AW6
CYC6
t
DS6
t
DH6
C
=100pF
ACC6
L
OH6
[V
Condition
t
AH6
AW6
CYC6
t
DS6
t
DH6
C
=100pF
ACC6
L
OH6
) ≤ (
t
t
t
–
–
f
CYC6
EWLW
EWHW
.
DD
EPSON
10. DC CHARACTERISTICS
=2.7V to 4.5V, Ta=–40 to +85°C]
DD
Specification value
Min.
Max.
0
—
0
—
500
—
40
—
15
—
—
140
10
100
120
—
60
—
60
—
60
—
=1.8V to 2.7V, Ta=–40 to +85°C]
DD
Specification value
Min.
Max.
0
—
0
—
1000
—
80
—
30
—
—
280
10
200
240
—
120
—
120
—
120
—
) ≤ (
t
t
) or (t
+t
–
r
f
CYC6
EWLR
Unit
ns
Unit
ns
t
–
).
EWHR
53
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