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Table 27
Item
Address hold time
Address setup time
System cycle time
Control LOW pulse width (Write)
Control LOW pulse width (Read)
Control HIGH pulse width (Write)
Control HIGH pulse width (Read)
Data setup time
Data hold time
RD access time
Output disable time
Table 28
Item
Address hold time
Address setup time
System cycle time
Control LOW pulse width (Write)
Control LOW pulse width (Read)
Control HIGH pulse width (Write)
Control HIGH pulse width (Read)
Data setup time
Data hold time
RD access time
Output disable time
*1. This is the case of accessing by WR and RD when CS1 = LOW.
*2. This is the case of accessing by CS1 when WR and RD = LOW.
*3
The rise and fall times (
time at high speed, they are specified for (
*4
All timings are specified based on the 20 and 80% of V
t
t
*5
and
are specified for the overlap period when CS1 is at LOW (CS2= HIGH) level and WR, RD are
CCLW
CCLR
at the LOW level.
S1D15710 Series (Rev. 1.1c)
Signal
Symbol
A0
t
AH8
t
AW8
A0
t
CYC8
WR
t
CCLW
RD
t
CCLR
WR
t
CCHW
RD
t
CCHR
D0 to D7
t
DS8
t
DH8
t
ACC8
t
OH8
Signal
Symbol
A0
t
AH8
t
AW8
A0
t
CYC8
WR
t
CCLW
RD
t
CCLR
WR
t
CCHW
RD
t
CCHR
D0 to D7
t
DS8
t
DH8
t
ACC8
t
OH8
t
t
and
) of the input signal are specified for less than 15 ns. When using the system cycle
r
f
) ≤ (
t
t
+
r
f
[V
DD
Condition
C
=100pF
L
[V
DD
Condition
C
=100pF
L
t
t
t
–
–
CYC8
CCLW
CCHW
.
DD
EPSON
10. DC CHARACTERISTICS
=2.7V to 4.5V, Ta=–40 to +85°C]
Specification value
Min.
Max.
0
—
0
—
500
—
60
—
120
—
60
—
60
—
40
—
15
—
—
140
10
100
=1.8V to 2.7V, Ta=–40 to +85°C]
Specification value
Min.
Max.
0
—
0
—
1000
—
120
—
240
—
120
—
120
—
80
—
30
—
—
280
10
200
) ≤ (
t
t
t
t
) or (
+
–
r
f
CYC8
CCLR
Unit
ns
Unit
ns
t
–
).
CCHR
51
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