C Board; 3-4-1.A/D Converter Unit; 3-4-2.Scan Converter; 3-4-2-1.Internal Block Diagram - Sony VPL-VW12HT Service Manual

3-4. C Board

3-4-1. A/D Converter Unit
IC5108 (AD9884A) is a maximum 140MS/s 8 bit x 3 color
A/D converter containing a PLL and clamp amplifier.
It is controlled by an I2C signal (SDA, SCL: Slave address
98HEX) from PW264.
Control of dot phase and H size is obtained by controlling
the clock generator via the I2C line, in accordance with
settings appropriate for the input signal.
The CLAMP and VSYNC (COAST) from the Q board are
input as pulses of positive polarity, while HSYNC is input
as pulses of negative polarity.
Digital OUT is demultiplexed so ODD/EVEN pixel data are
output in parallel.
At this time a _ sampling clock is also output for DATACK.
AD9884A
RIN
CLAMP
R IN
CLAMP
R IN
CLAMP
CLOCK
HSYNC
GENERATOR
COASR
CLAMP
CKINV
CKEXT
0.15V
FILT SOGIN SOGOUT SDA SCL
To reduce noise, the analog power supply VD of IC5108
(AD9884A) is stabilized and supplied by IC5101.
To further stabilize the PLL power supply (PVD), it is
supplied from IC5120 LP2985-3 with which use can be
made of a ceramic capacitor as the output capacitor.
3-14
8
R OUTA
8
A/D
8
R OUTB
8
G OUTA
8
A/D
8
G OUTB
8
B OUTA
8
A/D
8
B OUTB
2
DATACK
HSOUT
CONTROL REF REFIN
A0 A1 PWRDN REFOUT
3-4-2. SCAN Converter
IC5202 (SCAN CONVERTER) inputs the RGB signals
produced though digital conversion by IC5108 (AD9884A),
converts them to signals appropriate for the panel resolution
(WXGA: 1366 x 768) which it then outputs.
The OSD signals are also overlayed in this IC.
3-4-2-1. Internal Block Diagram (Simplified
diagram: Unused parts omitted)
Micro Processor
Grafics Port
8
GRE
8
GGE
8
GBE
8
GRO
8 Memory
GGO
SDRAM
8
GBO
GHS
GVS
GSOG
GCLK
GREF
GFBK
GHSFOUT
GBLKSPL
Processor
GCOAST
3-4-2-2. Graphics Port Block
8
8
8
8
8
IC5108 8
AD9884A
H SYNC
IC5201
TC7W125
Buffer
V SYNC
The graphics port subjects digital signals input in parallel
from IC5108 (AD9884A) to multiprocessing then sends the
data to internal SDRAM. It also generates pulses etc. that
control the IC5108 (AD9884A) PLL section using the H,V
sync input from the Q board.
The graphics port phase compares the H,V Sync and
discriminates between interlaced and non-interlaced sync.
A0~19
D0~15
Display Port
8
DRE
8
DGE
8
DBE
8
DRO
8
DGO
8
DBO
DHS
DVS
DCLK
OSD
Graphics Port
GRE
GGE
GBE
GRO
GGO
GBO
GCLK Memory
GREF
GFBK
GHSFOUT
GSOG
GHS
GVS
VPL-VW12HT