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3.4.1 Bank 0/1, 2/3, 4/5 DRAM Timing
DRAM timing is controlled by the DRAM timing registers. The timings programmed into this register
are dependent on the system design. The slower timing may be required in certain system designs
to support loose layouts or slower memory. Options are SDRAM 10ns, SDRAM 8ns, Normal,
Medium, Fast, Turbo.
3.4.2 SDRAM Cycle Length
This item allows you to set the SDRAM Latency Timer. Options are 2, 3.
3.4.3 DRAM Clock
This item allows you to set the DRAM Clock. Options are Host CLK or HCLK-33M. You must set
DRAM Clock as 66MHz if EDO RAM was installed on board. Please set the item according to the
Host (CPU) Clock and DRAM Clock.
3.4.4 Memory Hole
Enabling this feature reserves 15MB to 16MB memory address space to ISA expansion cards that
specifically require this setting. This makes the memory from 15MB and up unavailable to the
system. Expansion cards can only access memory up to 16MB.
3.4.5 Read Around write
DRAM optimization feature: If a memory read is addressed to a location whose latest write is being
held in a buffer before being written to memory, the read is satisfied through the buffer contents,
and the read is not sent to the DRAM.
3.4.6 Concurrent PCI/Host
When Disabled, CPU bus will be occupied during the entire PCI operation period.
3.4.7 System BIOS Cacheable
Allows the system BIOS to be cached for faster system performance.
3.4.8 Video BIOS Cacheable
Allows the video BIOS to be cached for faster video performance.
3.4.9 Video RAM Cacheable
Enabled allows caching of the video RAM, resulting in better system performance. However, if any
program writes to this memory area, a system error may result.
3.4.10 AGP Aperture Size
Choose 4, 8, 16, 32, 64, 128MB. Memory-mapped, graphics data structures can reside in the
Graphics Aperture.
3.4.11 AGP-2X Mode
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