Changes To Figure 16 And Adc Section And Figure 18 - Analog Devices AN-951 Application Note

AN-951
Input Driven by Control Port
In this mode, the GPIO pin is bypassed, and the core reads its
value from the associated register. This register's value can be
written or read via the control port. This mode is useful for
controlling elements of the signal flow with an external host
controller. The core reads the input value from its associated
register once per audio frame.
ADC
DEBOUNCE
GPIO PIN REGISTER
CONTROL
Figure 16. Input Driven by Control Port Data Flow
Output Driven by Control Port
In this mode, the signal flow in the core does not affect the
output of the associated GPIO pin, and the pin reads its output
value from the associated register. This register's value can be
written or read via the control port.
This mode is useful for directly controlling circuitry, such as an
LED, connected to the GPIO pins with an external host control-
ler. The GPIO pin reads the output value from its associated
register once per audio frame.
ADC
DEBOUNCE
GPIO PIN REGISTER
CONTROL
Figure 17. Output Driven by Control Port Data Flow
DSP CORE
PORT
DSP CORE
PORT
ADC
When the pin is set in ADC mode, it is used as one of the multi-
plexed inputs to the auxiliary ADC. On the ADAU170x, the
invert bit should be activated for proper ADC function. The
core reads the input value from the ADC once per audio frame,
although the ADC sampling rate is dependent on the particular
SigmaDSP being used.
GPIO PIN
Rev. A | Page 6 of 20
Application Note
ADC
DEBOUNCE
REGISTER DSP CORE
CONTROL
PORT
Figure 18. ADC Data Flow