Adjust The Pwm Switching Frequency; Multiple Unit Evaluation - Analog Devices ADN8831 Application Note

Application Note
2. When the compensation loop is stable, it is possible to adjust
the component values in the network to decrease the overall
loop response time. This is accomplished by slowly decreasing
CI, increasing RP, decreasing RD, increasing CD, and decreas-
ing RI. Adjust these such that the output at Pin OUT2 has
a fast rise and fall time with little or no overshoot. In applica-
tions where fast response time is critical, allow for a small
amount of overshoot (10% to 20%).
3. After tuning the compensation network to satisfactory values,
it is recommended to replace the tunable compensation net-
work components with the discrete components to be used
in the future system and repeat the test. After soldering the
discrete components, turn off the tunable compensation net-
work components by placing all the switches into the lower
position.
4. The capacitors used in the compensation network should be
multilayer ceramic capacitors of X7R material. This type of
capacitor maintains a stable capacitance over temperature and
bias drifts. X7R type capacitors also have a very low leakage
current and low noise.
Typical performance for a butterfly-packaged laser with a
settling time of 1°C change in setpoint temperature is
approximately 0.2 second to 1 second; for a large mass laser
head of 1 W to 3 W, the settling time is about 5 seconds to
20 seconds. For more details of the temperature compensation
network, see the ADN8831 data sheet.

ADJUST THE PWM SWITCHING FREQUENCY

The ADN8831 evaluation board is default set to a free-run
PWM clock at 1 MHz. To modify R
switching frequency (see Figure 7). Reducing the frequency
of the PWM switching frequency improves the system power
efficiency, but requires the use of a large physical size LC filter
inductor and capacitors.
For telecommunication applications, the recommended setting
(default) is 1 MHz for the switching frequency. However, for
applications where efficiency is critical, a 500 kHz clock is
an option.
Table 3. Switching Frequencies vs. R
f
SWITCH
250 kHz
500 kHz
750 kHz
1 MHz
, adjust the PWM
FREQ
FREQ
R
FREQ
484 kΩ
249 kΩ
168 kΩ
118 kΩ
Rev. C | Page 7 of 12
ADN8831
COMPOSC
FREQ
SYNCI/SD
Figure 7. Switching Frequencies

MULTIPLE UNIT EVALUATION

The ADN8831 can drive one TEC or, in a multiple unit configure-
tion, can drive multiple TECs. Details for connecting multiple
devices together are available in the ADN8831 data sheet. Access to
the connection pins for synchronizations and phase assignment
is available through the PHASE, SYNCO, and SYNCIN solder
pads located in the center of the evaluation board.
If the system noise is significant, change the 1 MΩ resistors
of the slaves to 15% (136 kΩ) higher than the 118 kΩ recom-
mended for the master ADN8831. For details, contact your
local Analog Devices, Inc. sales office.
ADN8831
MASTER
COMPOSC
FREQ
SYNCI/SD
PHASE
SYNCO
10kΩ
ADN8831
SLAVE
COMPOSC
SYNCI/SD
ADN8831
SLAVE
COMPOSC
SYNCI/SD
Figure 8. Multiple Unit Configuration
AN-695
LP3
PV
DD
1nF
0.1µF
1kΩ
R
FREQ
V
DD
V
DD
118kΩ
V
DD
NC
V
DD
1nF
0.1µF
1kΩ
1MΩ
FREQ
V
PHASE
PHASE
1nF
0.1µF
1kΩ
1MΩ
FREQ
V
PHASE
PHASE