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Manuals and User Guides for Nuvoton NUC126LE4AE. We have
1
Nuvoton NUC126LE4AE manual available for free PDF download: Technical Reference Manual
Nuvoton NUC126LE4AE Technical Reference Manual (943 pages)
Brand:
Nuvoton
| Category:
Microcontrollers
| Size: 10 MB
Table of Contents
Table of Contents
2
General Description
19
Key Feature and Application
19
Table 1.1-1 Key Features Support Table
19
Features
20
Numicro ® NUC126 Features
20
Abbreviations
28
Table 3.1-1 List of Abbreviations
29
Parts Information List and Pin Configuration
30
Numicro ® NUC126 Selection Guide
30
Numicro ® NUC126 Naming Rule
30
Numicro ® NUC126 USB Series (M452 Compatible) Selection Guide
31
Pin Configuration
32
Numicro ® NUC126 USB Series QFN48 Pin Diagram
32
Figure 4.2-1 Numicro ® NUC126 USB Series QFN 48-Pin Diagram
32
Numicro ® NUC126 USB Series LQFP48 Pin Diagram
33
Figure 4.2-2 Numicro ® NUC126 USB Series LQFP 48-Pin Diagram
33
Numicro ® NUC126 USB Series LQFP64 Pin Diagram
34
Figure 4.2-3 Numicro ® NUC126 USB Series LQFP 64-Pin Diagram
34
Numicro ® NUC126 USB Series LQFP100 Pin Diagram
35
Figure 4.2-4 Numicro ® NUC126 USB Series LQFP 100-Pin Diagram
35
Pin Description
36
NUC126 USB Series Pin Description
36
GPIO Multi-Function Pin Summary
53
Table 4.3-1 NUC126 GPIO Multi-Function Table
68
Block Diagram
69
Numicro ® NUC126 Block Diagram
69
Figure 5.1-1 Numicro NUC126 Block Diagram
69
Functional Description
70
ARM ® Cortex ® -M0 Core
70
Figure 6.1-1 Functional Block Diagram
70
System Manager
72
Overview
72
System Reset
72
Figure 6.2-1 System Reset Sources
73
Table 6.2-1 Reset Value of Registers
75
Figure 6.2-2 Nreset Reset Waveform
76
Figure 6.2-3 Power-On Reset (POR) Waveform
76
Figure 6.2-4 Low Voltage Reset (LVR) Waveform
77
Figure 6.2-5 Brown-Out Detector (BOD) Waveform
78
Power Modes and Wake-Up Sources
79
Table 6.2-2 Power Mode Difference Table
79
Figure 6.2-6 Numicro ® NUC126 Power Mode State Machine
80
Table 6.2-3 Clocks in Power Modes
81
System Power Distribution
82
Table 6.2-4 Condition of Entering Power-Down Mode Again
82
Figure 6.2-7 Numicro ® NUC126 Power Distribution Diagram
83
System Memory Map
84
Table 6.2-5 Address Space Assignments for On-Chip Controllers
85
SRAM Memory Orginization
86
Figure 6.2-8 SRAM Block Diagram
86
Register Lock
87
Auto Trim
87
Figure 6.2-9 SRAM Memory Organization
87
UART1_TXD Modulation with PWM
88
Figure 6.2-10 UART1_TXD Modulated with PWM Channel
88
Voltage Detector (VDET)
89
Figure 6.2-11 VDET Block Diagram
89
Register Map
90
Register Description
92
System Timer (Systick)
133
Nested Vectored Interrupt Controller (NVIC)
138
Table 6.2-6 Exception Model
139
Table 6.2-7 Interrupt Number Table
140
System Control
161
Clock Controller
169
Overview
169
Table 6.3-1 Clock Stable Count Value Table
169
Figure 6.3-1 Clock Generator Block Diagram
170
Figure 6.3-2 Clock Generator Global View Diagram
171
System Clock and Systick Clock
172
Figure 6.3-3 System Clock Block Diagram
172
Peripherals Clock
173
Figure 6.3-4 HXT Stop Protect Procedure
173
Figure 6.3-5 Systick Clock Control Block Diagram
173
Power-Down Mode Clock
174
Clock Output
174
Figure 6.3-6 Clock Source of Clock Output
174
Figure 6.3-7 Clock Output Block Diagram
175
Register Map
176
Register Description
177
Table 6.3-2 Power-Down Mode Control Table
179
Flash Memeory Controller (FMC)
205
Overview
205
Features
205
Block Diagram
206
Figure 6.4-1 Flash Memory Controller Block Diagram
206
Functional Description
207
Figure 6.4-2 Data Flash
208
Figure 6.4-3 SPROM Security Mode
213
Figure 6.4-4 Flash Memory Map
214
Figure 6.4-5 System Memory Map with IAP Mode
215
Figure 6.4-6 APROM/LDROM Boot with IAP Mode
216
Figure 6.4-7 VECMAP Setting Example in IAP Mode
216
Figure 6.4-8 System Memory Map Without IAP Mode
217
Table 6.4-1 Boot Source Selection Table
218
Table 6.4-2 ISP Command List
219
Figure 6.4-9 ISP Procedure Example
220
Figure 6.4-10 Example for Accelerating Interrupt by VECMAP
221
Figure 6.4-11 ISP 32-Bit Programming Procedure
222
Table 6.4-3 FMC Control Registers for Flash Programming
222
Figure 6.4-12 ISP 64-Bit Programming Procedure
223
Figure 6.4-13 Firmware in SRAM for Multi-Word Programming
224
Figure 6.4-14 Multi-Word Programming Flow
225
Figure 6.4-15 CRC-32 Checksum Calculation
226
Figure 6.4-16 CRC-32 Checksum Calculation Flow
227
Figure 6.4-17 All-One Verification Flow
228
Register Map
229
Register Description
230
Analog Comparator Controller (ACMP)
247
Overview
247
Features
247
Block Diagram
248
Figure 6.5-1 Analog Comparator Block Diagram
248
Basic Configuration
249
Functional Description
249
Figure 6.5-2 Comparator Hysteresis Function of ACMP0
250
Figure 6.5-3 Window Latch Mode of ACMP0
250
Figure 6.5-4 Filter Function Example
251
Figure 6.5-5 Comparator Controller Interrupt
251
Figure 6.5-6 Comparator Reference Voltage Block Diagram
252
Figure 6.5-7 Example Connection of Window Compare Mode
253
Figure 6.5-8 Example of Window Compare Mode
253
Register Map
254
Register Description
255
Analog-To-Digital Converter (ADC)
262
Overview
262
Features
262
Block Diagram
263
Basic Configuration
263
Figure 6.6-1 AD Controller Block Diagram
263
Functional Description
264
Figure 6.6-2 ADC Peripheral Clock Control
265
Figure 6.6-3 Single Mode Conversion Timing Diagram
266
Figure 6.6-4 Burst Mode Conversion Timing Diagram
267
Figure 6.6-5 Single-Cycle Scan Mode on Enabled Channels Timing Diagram
268
Figure 6.6-6 Continuous Scan Mode on Enabled Channels Timing Diagram
269
Figure 6.6-7 A/D Conversion Result Monitor Logic Diagram
270
Figure 6.6-8 A/D Controller Interrupt
271
Register Map
272
Register Description
274
Figure 6.6-9 Conversion Result Mapping Diagram of ADC Single-End Input
275
Figure 6.6-10 Conversion Result Mapping Diagram of ADC Differential Input
276
CRC Controller (CRC)
289
Overview
289
Features
289
Block Diagram
289
Figure 6.7-1 CRC Generator Block Diagram
289
Basic Configuration
290
Functional Description
290
Figure 6.7-2 CHECKSUM Bit Order Reverse Functional Block
290
Figure 6.7-3 Write Data Bit Order Reverse Functional Block
291
Register Map
292
Register Description
293
External Bus Interface (EBI)
298
Overview
298
Features
298
Block Diagram
299
Basic Configuration
299
Figure 6.8-1 EBI Block Diagram
299
Functional Description
300
Table 6.8-1 EBI Memory Mapping of Bank0 and Bank1
300
Figure 6.8-2 Connection of 16-Bit Device with 16-Bit EBI Data Width
301
Figure 6.8-3 Connection of 8-Bit Device with 8-Bit EBI Data Width
302
Table 6.8-2 EBI Timing Control Setting Table
303
Figure 6.8-4 Timing Control Waveform for 16-Bit Data Width
304
Figure 6.8-5 Timing Control Waveform for 8-Bit Data Width
305
Figure 6.8-6 Timing Control Waveform for Insert Idle Cycle
306
Figure 6.8-7 Timing Control Waveform for Continuous Data Access Mode
307
Register Map
308
Register Description
309
General Purpose I/O (GPIO)
313
Overview
313
Features
313
Block Diagram
314
Figure 6.9-1 GPIO Controller Block Diagram
314
Basic Configuration
315
Functional Description
315
Figure 6.9-2 GPIO Clock Control Diagram
315
Register Map
318
Register Description
321
Hardware Divider (HDIV)
336
Overview
336
Features
336
Blcok Diagram
336
Basic Configuration
336
Functional Description
336
Figure 6.10-1 Hardware Divider Block Diagram
336
Register Map
338
Register Description
339
C Serial Interface Controller (I C)
344
Overview
344
Features
344
Block Diagram
345
Basic Configuration
345
Figure 6.11-1 I 2 C Controller Block Diagram
345
Functional Description
346
Figure 6.11-2 I 2 C Bus Timing
346
Figure 6.11-3 I 2 C Protocol
347
Figure 6.11-4 START and STOP Conditions
347
Figure 6.11-5 Bit Transfer on the I C Bus
348
Figure 6.11-6 Acknowledge on the I C Bus
348
Figure 6.11-7 Master Transmits Data to Slave by 7-Bit
349
Figure 6.11-8 Master Reads Data from Slave by 7-Bit
349
Figure 6.11-9 Control I C Bus According to the Current I C Status
350
Figure 6.11-10 Master Transmitter Mode Control Flow
350
Figure 6.11-11 Master Receiver Mode Control Flow
351
Figure 6.11-12 Slave Mode Control Flow
352
Figure 6.11-13 GC Mode
353
Figure 6.11-14 Arbitration Lost
354
Figure 6.11-15 Timing of Two-Level Buffer Transmit in Master Write
355
Figure 6.11-16 Timing of Two-Level Buffer Transmit in Slave Read
355
Figure 6.11-17 Setup Time Wrong Adjustment
356
Figure 6.11-18 Hold Time Wrong Adjustment
356
Table 6.11-1 Relationship between I 2 C Baud Rate and PCLK
356
Figure 6.11-19 I 2 C Data Shifting Direction
357
Table 6.11-2 I 2 C Status Code Description
358
Figure 6.11-20 I 2 C Time-Out Count Block Diagram
359
Figure 6.11-21 I 2 C Wake-Up Related Signals Waveform
360
Figure 6.11-22 EEPROM Random Read
361
Figure 6.11-23 Protocol of EEPROM Random Read
361
Register Map
362
Register Description
363
PDMA Controller (PDMA)
376
Overview
376
Features
376
Block Diagram
376
Basic Configuration
376
Figure 6.12-1 PDMA Controller Block Diagram
376
Functional Description
377
Figure 6.12-2 Descriptor Table Entry Structure
377
Table 6.12-1 Channel Priority Table
377
Figure 6.12-3 Descriptor Table Operation in Basic Mode
378
Figure 6.12-4 Descriptor Table Link List Structure
380
Figure 6.12-5 Scatter-Gather Mode Finite State Machine
380
Figure 6.12-6 Example of Single Transfer Type and Burst Transfer Type in Basic Mode
382
Figure 6.12-7 Example of PDMA Channel 0 Time-Out Counter Operation
383
Register Map
384
Register Description
386
PWM Generator and Capture Timer (PWM)
413
Overview
413
Features
413
Block Diagram
415
Figure 6.13-1 PWM Generator Overview Block Diagram
415
Figure 6.13-2 PWM System Clock Source Control
415
Figure 6.13-3 PWM Clock Source Control
416
Table 6.13-1 PWM System Clock Source Control Registers Setting Table
416
Figure 6.13-4 PWM Independent Mode Architecture Diagram
417
Basic Configuration
418
Figure 6.13-5 PWM Complementary Mode Architecture Diagram
418
Functional Description
419
Figure 6.13-6 PWM0_CH0 Prescaler Waveform in up Counter Type
420
Figure 6.13-7 PWM up Counter Type
420
Figure 6.13-8 PWM down Counter Type
421
Figure 6.13-9 PWM Up-Down Counter Type
421
Figure 6.13-10 PWM Compared Point Events in Up-Down Counter Type
422
Figure 6.13-11 PWM Double Buffering Illustration
423
Figure 6.13-12 Period Loading in Up-Count Mode
424
Figure 6.13-13 Immediately Loading in Up-Count Mode
425
Figure 6.13-14 Window Loading in Up-Count Mode
426
Figure 6.13-15 Center Loading in Up-Down-Count Mode
427
Figure 6.13-16 PWM One-Shot Mode Output Waveform
428
Figure 6.13-17 PWM Pulse Generation
429
Figure 6.13-18 PWM 0% to 100% Pulse Generation
429
Table 6.13-2 PWM Pulse Generation Event Priority for Up-Counter
429
Figure 6.13-19 PWM Independent Mode Waveform
430
Table 6.13-3 PWM Pulse Generation Event Priority for Down-Counter
430
Table 6.13-4 PWM Pulse Generation Event Priority for Up-Down-Counter
430
Figure 6.13-20 PWM Complementary Mode Waveform
431
Figure 6.13-21 PWM Group Function Waveform
432
Figure 6.13-22 PWM SYNC_IN Noise Filter Block Diagram
432
Figure 6.13-23 PWM Counter Synchronous Function Block Diagram
433
Figure 6.13-24 PWM Synchronous Function with Synchronize Source from SYNC_IN Signal
434
Figure 6.13-25 Pwmx_Ch0 Output Control in Independent Mode
434
Figure 6.13-26 Pwmx_Ch0 and Pwmx_Ch1 Output Control in Complementary Mode
435
Figure 6.13-27 Dead-Time Insertion
435
Figure 6.13-28 Illustration of Mask Control Waveform
436
Figure 6.13-29 Brake Noise Filter Block Diagram
437
Figure 6.13-30 Brake Block Diagram for Pwmx_Ch0 and Pwmx_Ch1 Pair
438
Figure 6.13-31 Edge Detector Waveform for Pwmx_Ch0 and Pwmx_Ch1 Pair
439
Figure 6.13-32 Level Detector Waveform for Pwmx_Ch0 and Pwmx_Ch1 Pair
439
Figure 6.13-33 Brake Source Block Diagram
440
Figure 6.13-34 Brake System Fail Block Diagram
440
Figure 6.13-35 PWM LEB Function Waveform
441
Figure 6.13-36 Initial State and Polarity Control with Rising Edge Dead-Time Insertion
442
Figure 6.13-37 Pwmx_Ch0 and Pwmx_Ch1 Pair Accumulate Interrupt Waveform
443
Figure 6.13-38 Pwmx_Ch0 and Pwmx_Ch1 Pair Interrupt Architecture Diagram
444
Figure 6.13-39 Pwmx_Ch0 and Pwmx_Ch1 Pair Trigger ADC Block Diagram
445
Figure 6.13-40 PWM Trigger ADC in Up-Down Counter Type Timing Waveform
446
Figure 6.13-41 Pwmx_Ch0 Capture Block Diagram
447
Figure 6.13-42 Capture Operation Waveform
448
Figure 6.13-43 Capture PDMA Operation Waveform of Channel 0
449
Register Map
450
Register Description
454
Real Time Clock (RTC)
518
Overview
518
Features
518
Block Diagram
518
Basic Configuration
519
Functional Description
519
Figure 6.14-1 RTC Block Diagram
519
Table 6.14-1 RTC Read/Write Access Attribute
520
Table 6.14-212/24-Hour Time Scale Selection
521
Table 6.14-3 Registers Default Value after Powered on
522
Table 6.14-4 Registers Power Domain
523
Figure 6.14-2 Backup I/O Control Diagram
524
Register Map
525
Register Description
526
Smart Card Host Interface (SC)
546
Overview
546
Features
546
Block Diagram
546
Figure 6.15-1 SC Clock Control Diagram
547
Figure 6.15-2 SC Controller Block Diagram
547
Basic Configuration
548
Table 6.15-1 SC Host Controller Pin Description
548
Table 6.15-2 UART Pin Description
548
Functional Description
549
Figure 6.15-3 SC Data Character
549
Figure 6.15-4 SC Activation Sequence
550
Figure 6.15-5 SC Warm Reset Sequence
551
Figure 6.15-6 SC Deactivation Sequence
552
Figure 6.15-7 Basic Operation Flow
553
Figure 6.15-8 Initial Character TS
554
Figure 6.15-9 SC Error Signal
554
Figure 6.15-10 Transmit Direction Block Guard Time Operation
557
Figure 6.15-11 Receive Direction Block Guard Time Operation
557
Table 6.15-3 Timer0/Timer1/Timer2 Operation Mode
557
Figure 6.15-12 Extra Guard Time Operation
558
Register Map
559
Register Description
560
Serial Peripheral Interface (SPI)
586
Overview
586
Features
586
6.16.3 Block Diagram
587
Basic Configuration
587
Figure 6.16-1 SPI Block Diagram (SPI0/1)
587
Functional Description
589
Figure 6.16-2 SPI Peripheral Clock
589
Table 6.16-1 SPI/I 2 S Interface Controller Pin
589
Figure 6.16-3 SPI Full-Duplex Master Mode Application Block Diagram
590
Figure 6.16-4 SPI Full-Duplex Slave Mode Application Block Diagram
590
Figure 6.16-532-Bit in One Transaction
591
Figure 6.16-6 Automatic Slave Selection (SSACTPOL = 0, SUSPITV > 0X2)
592
Figure 6.16-7 Automatic Slave Selection (SSACTPOL = 0, SUSPITV < 0X3)
592
Figure 6.16-8 Byte Reorder Function
593
Figure 6.16-9 Timing Waveform for Byte Suspend
593
Figure 6.16-10 SPI Half-Duplex Master Mode Application Block Diagram
594
Figure 6.16-11 SPI Half-Duplex Slave Mode Application Block Diagram
594
Figure 6.16-12 FIFO Threshold Comparator
595
Figure 6.16-13 Transmit FIFO Buffer Example
596
Figure 6.16-14 Receive FIFO Buffer Example
597
Figure 6.16-15 TX Underflow Event and Slave under Run Event
597
Figure 6.16-16 Slave Mode Bit Count Error
598
Figure 6.16-17 I 2 S Data Format Timing Diagram
599
Figure 6.16-18 MSB Justified Data Format Timing Diagram
600
Figure 6.16-19 PCM Mode a Timing Diagram
600
Figure 6.16-20 PCM Mode B Timing Diagram
600
Figure 6.16-21 FIFO Contents for Various I
601
Modes
601
Timing Diagram
602
Figure 6.16-22 SPI Timing in Master Mode
602
Figure 6.16-23 SPI Timing in Master Mode (Alternate Phase of Spix_Clk)
602
Figure 6.16-24 SPI Timing in Slave Mode
603
Figure 6.16-25 SPI Timing in Slave Mode (Alternate Phase of Spix_Clk)
603
Programming Examples
604
Register Map
606
Register Description
607
Timer Controller (TMR)
626
Overview
626
Features
626
Block Diagram
628
Figure 6.17-1 Timer Controller Block Diagram
628
Figure 6.17-2 Clock Source of Timer Controller
629
Figure 6.17-3 PWM Generator Overview Block Diagram
630
Figure 6.17-4 PWM System Clock Source Control
630
Figure 6.17-5 PWM Counter Clock Source Control
631
Figure 6.17-6 PWM Independent Mode Architecture Diagram
631
Basic Configuration
632
Figure 6.17-7 PWM Complementary Mode Architecture Diagram
632
Timer Functional Description
633
Figure 6.17-8 Continuous Counting Mode
635
Figure 6.17-9 External Capture Mode
636
Figure 6.17-10 External Reset Counter Mode
636
Figure 6.17-11 Internal Timer Trigger
637
PWM Functional Description
638
Figure 6.17-12 Inter-Timer Trigger Capture Timing
638
Figure 6.17-13 PWM Prescale Waveform in up Count Type
638
Figure 6.17-14 PWM up Count Type
639
Figure 6.17-15 PWM down Count Type
639
Figure 6.17-16 PWM Up-Down Count Type
640
Figure 6.17-17 PWM Comparator Events in Up-Down Count Type
641
Figure 6.17-18 Period Loading Mode with up Count Type
642
Figure 6.17-19 Immediately Loading Mode with up Count Type
643
Figure 6.17-20 PWM Pulse Generation in Up-Down Count Type
643
Figure 6.17-21 PWM 0% to 100% Duty Cycle in up Count Type and Up-Down Count Type
644
Table 6.17-1 PWM Pulse Generation Event Priority in up Count Type
644
Table 6.17-2 PWM Pulse Generation Event Priority in down Count Type
644
Table 6.17-3 PWM Pulse Generation Event Priority in Up-Down Count Type
644
Figure 6.17-22 PWM Independent Mode Output Waveform
645
Figure 6.17-23 PWM Complementary Mode Output Waveform
645
Figure 6.17-24 Pwmx_Ch0 Output Control in Independent Mode
645
Figure 6.17-25 Pwmx_Ch0 and Pwmx_Ch1 Output Control in Complementary Mode
646
Figure 6.17-26 Dead-Time Insertion
646
Figure 6.17-27 PWM Output Mask Control Waveform
647
Figure 6.17-28 Brake Pin Noise Filter Block Diagram
647
Figure 6.17-29 Brake Event Block Diagram for Pwmx_Ch0 and Pwmx_Ch1
648
Figure 6.17-30 Edge Detector Brake Waveform for Pwmx_Ch0 and Pwmx_Ch1
649
Figure 6.17-31 Level Detector Brake Waveform for Pwmx_Ch0 and Pwmx_Ch1
650
Figure 6.17-32 Brake Source Block Diagram
651
Figure 6.17-33 System Fail Brake Block Diagram
651
Figure 6.17-34 Pwmx_Ch0 and Pwmx_Ch1 Polarity Control with Dead-Time Insertion
652
Figure 6.17-35 PWM Interrupt Architecture Diagram
653
Figure 6.17-36 PWM Trigger ADC Block Diagram
653
6.17.7 Register Map
654
Register Description
659
USB Device Controller (USBD)
703
Overview
703
Features
703
Block Diagram
704
Basic Configuration
704
Functional Description
704
Figure 6.18-1 USB Block Diagram
704
Figure 6.18-2 WKIDLE Interrupt Operation Flow
706
Figure 6.18-3 Endpoint SRAM Structure
707
Figure 6.18-4 Setup Transaction Followed by Data in Transaction
707
Figure 6.18-5 Data out Transfer
708
Register Map
710
6.18.7 Register Description
712
6.19 USCI - Universal Serial Control Interface Controller
731
Overview
731
Features
731
Block Diagram
731
Functional Description
731
Figure 6.19-1 USCI Block Diagram
731
Figure 6.19-2 Input Conditioning for Uscix_Dat[1:0] and Uscix_Ctl[1:0]
732
Table 6.19-1 Input Signals for Different Protocols
732
Figure 6.19-3 Input Conditioning for Uscix_Clk
733
Table 6.19-2 Output Signals for Different Protocols
733
Figure 6.19-4 Block Diagram of Data Buffering
734
Figure 6.19-5 Data Access Structure
735
Figure 6.19-6 Transmit Data Path
735
Figure 6.19-7 Receive Data Path
736
Figure 6.19-8 Protocol-Relative Clock Generator
737
Figure 6.19-9 Basic Clock Divider Counter
738
Figure 6.19-10 Block of Timing Measurement Counter
738
Figure 6.19-11 Sample Time Counter
739
Figure 6.19-12 Event and Interrupt Structure
740
Table 6.19-3 Data Transfer Events and Interrupt Handling
740
Table 6.19-4 Protocol-Specific Events and Interrupt Handling
741
6.20 USCI - UART Mode
742
Overview
742
Features
742
Block Diagram
742
Figure 6.20-1 USCI UART Mode Block Diagram
742
Basic Configuration
743
Functional Description
744
Figure 6.20-2 UART Signal Connection for Full-Duplex Communication
745
Table 6.20-1 Input Signals for UART Protocols
745
Figure 6.20-3 UART Standard Frame Format
746
Table 6.20-2 Output Signals for Different Protocols
746
Figure 6.20-4 UART Bit Timing (Data Sample Time)
748
Figure 6.20-5 UART Auto Baud Rate Control
749
Figure 6.20-6 Incoming Data Wake-Up
750
Figure 6.20-7 Ncts Wake-Up Case 1
750
Figure 6.20-8 Ncts Wake-Up Case 2
751
6.20.6 Register Map
753
6.20.7 Register Description
754
6.21 USCI - SPI Mode
775
Overview
775
Features
775
Figure 6.21-1 SPI Master Mode Application Block Diagram
775
Figure 6.21-2 SPI Slave Mode Application Block Diagram
775
Block Diagram
776
Basic Configuration
776
Figure 6.21-3 USCI SPI Mode Block Diagram
776
Functional Description
778
Table 6.21-1 SPI Communication Signals
778
Figure 6.21-4 Wire Full-Duplex SPI Communication Signals (Master Mode)
779
Figure 6.21-5 Wire Full-Duplex SPI Communication Signals (Slave Mode)
779
Figure 6.21-6 SPI Communication with Different SPI Clock Configuration (Sclkmode=0X0)
780
Table 6.21-2 Serial Bus Clock Configuration
780
Figure 6.21-7 SPI Communication with Different SPI Clock Configuration (Sclkmode=0X1)
781
Figure 6.21-8 SPI Communication with Different SPI Clock Configuration (Sclkmode=0X2)
781
Figure 6.21-9 SPI Communication with Different SPI Clock Configuration (Sclkmode=0X3)
782
Figure 6.21-1016-Bit Data Length in One Word Transaction with MSB First Format
783
Figure 6.21-11 Word Suspend Interval between Two Transaction Words
783
Figure 6.21-12 Auto Slave Select (SUSPITV ≧ 0X3)
784
Figure 6.21-13 Auto Slave Select (SUSPITV < 0X3)
784
Figure 6.21-14 One Output Data Channel Half-Duplex (SPI Master Mode)
785
Figure 6.21-15 One Input Data Channel Half-Duplex (SPI Master Mode)
786
Figure 6.21-16 SPI Timing in Master Mode
788
Figure 6.21-17 SPI Timing in Master Mode (Alternate Phase of Serial Bus Clock)
788
Figure 6.21-18 SPI Timing in Slave Mode
789
Figure 6.21-19 SPI Timing in Slave Mode (Alternate Phase of Serial Bus Clock)
789
6.21.6 Register Map
792
6.21.7 Register Description
793
USCI - I C Mode
815
Overview
815
Features
815
Figure 6.22-1 I 2 C Bus Timing
815
6.22.3 Block Diagram
816
Basic Configuration
816
Figure 6.22-2 USCI I²C Mode Block Diagram
816
Functional Description
818
Figure 6.22-3 I 2 C Protocol
818
Figure 6.22-4 START and STOP Conditions
819
Figure 6.22-5 Bit Transfer on the I 2 C Bus
820
Figure 6.22-6 Acknowledge on the I 2 C Bus
820
Figure 6.22-7 Arbitration Lost
821
Figure 6.22-8 Control I C Bus According to Current I C Status
824
Figure 6.22-9 Master Transmits Data to Slave with a 7-Bit Address
825
Figure 6.22-10 Master Reads Data from Slave with a 7-Bit Address
825
Figure 6.22-11 Master Transmits Data to Slave by 10-Bit Address
825
Figure 6.22-12 Master Reads Data from Slave by 10-Bit Address
826
Figure 6.22-13 Master Transmitter Mode Control Flow with 7-Bit Address
826
Figure 6.22-14 Master Receiver Mode Control Flow with 7-Bit Address
827
Figure 6.22-15 Save Mode Control Flow with 7-Bit Address
828
Figure 6.22-16 GC Mode with 7-Bit Address
830
Table 6.22-1 Relationship between I 2 C Baud Rate and PCLK
831
Figure 6.22-17 Setup Time Wrong Adjustment
832
Figure 6.22-18 Hold Time Wrong Adjustment
832
Figure 6.22-19 I 2 C Time-Out Count Block Diagram
833
Figure 6.22-20 EEPROM Random Read
834
Figure 6.22-21 Protocol of EEPROM Random Read
834
6.22.6 Register Map
835
6.22.7 Register Description
836
UART Interface Controller (UART)
855
Overview
855
Features
855
Block Diagram
856
Figure 6.23-1 UART Clock Control Diagram
856
Figure 6.23-2 UART Block Diagram
856
Basic Configuration
858
Table 6.23-1 UART Interrupt
858
Table 6.23-2 UART Interface Controller Pin
858
Functional Description
860
Table 6.23-3 UART Controller Baud Rate Equation Table
860
Table 6.23-4 UART Controller Baud Rate Parameter Setting Example Table
861
Table 6.23-5 UART Controller Baud Rate Register Setting Example Table
861
Table 6.23-6 Baud Rate Compensation Example Table 1
862
Table 6.23-7 Baud Rate Compensation Example Table 2
862
Figure 6.23-3 Auto-Baud Rate Measurement
863
Figure 6.23-4 Transmit Delay Time Operation
864
Figure 6.23-5 UART Ncts Wake-Up Case1
864
Figure 6.23-6 UART Ncts Wake-Up Case2
865
Figure 6.23-7 UART Data Wake-Up
865
Figure 6.23-8 UART Received Data FIFO Reached Threshold Wake-Up
866
Figure 6.23-9 UART RS-485 AAD Mode Address Match Wake-Up
866
Figure 6.23-10 UART Received Data FIFO Threshold Time-Out Wake-Up
867
Table 6.23-8 UART Controller Interrupt Source and Flag List
869
Table 6.23-9 UART Line Control of Word and Stop Length Setting
869
Figure 6.23-11 Auto-Flow Control Block Diagram
870
Table 6.23-10 UART Line Control of Parity Bit Setting
870
Figure 6.23-12 UART Ncts Auto-Flow Control Enabled
871
Figure 6.23-13 UART Nrts Auto-Flow Control Enabled
871
Figure 6.23-14 UART Nrts Auto-Flow with Software Control
872
Figure 6.23-15 Irda Control Block Diagram
872
Figure 6.23-16 Irda TX/RX Timing Diagram
873
Figure 6.23-17 Structure of LIN Frame
874
Figure 6.23-18 Structure of LIN Byte
874
Table 6.23-11 LIN Header Selection in Master Mode
875
Figure 6.23-19 Break Detection in LIN Mode
876
Figure 6.23-20 LIN Frame ID and Parity Format
876
Figure 6.23-21 LIN Sync Field Measurement
878
Figure 6.23-22 UART_BAUD Update Sequence in AR Mode if SLVDUEN Is 1
879
Figure 6.23-23 UART_BAUD Update Sequence in AR Mode if SLVDUEN Is 0
879
Figure 6.23-24 RS-485 Nrts Driving Level in Auto Direction Mode
881
Figure 6.23-25 RS-485 Nrts Driving Level with Software Control
882
Figure 6.23-26 Structure of RS-485 Frame
883
6.23.6 Register Map
884
6.23.7 Register Description
886
Watchdog Timer (WDT)
919
Overview
919
Features
919
Block Diagram
919
Basic Configuration
919
Figure 6.24-1 Watchdog Timer Block Diagram
919
Functional Description
920
Figure 6.24-2 Watchdog Timer Clock Control
920
Table 6.24-1 Watchdog Timer Time-Out Interval Period Selection
920
Figure 6.24-3 Watchdog Timer Time-Out Interval and Reset Period Timing
921
6.24.6 Register Map
922
6.24.7 Register Description
923
Window Watchdog Timer (WWDT)
927
Overview
927
Features
927
Block Diagram
927
Figure 6.25-1 WWDT Block Diagram
927
Basic Configuration
928
Functional Description
928
Figure 6.25-2 WWDT Clock Control
928
Figure 6.25-3 WWDT Compare Match Interrupt When CMPDAT Is 0X3E
929
Table 6.25-1 WWDT Prescale Value Selection and Time-Out Period
929
Figure 6.25-4 WWDT Counter Reload and Reset Behavior
930
Table 6.25-2 CMPDAT Setting Limitation
930
6.25.6 Register Map
931
6.25.7 Register Description
932
Application Circuit
937
Package Dimensions
938
LQFP 100L (14X14X1.4 MM Footprint 2.0 MM)
938
LQFP 64L (7X7X1.4 MM Footprint 2.0 MM)
939
LQFP 48L (7X7X1.4 MM Footprint 2.0 MM)
940
QFN 48L (7X7X0.8 MM)
941
Revision History
942
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