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AT32F421C8T7
ARTERY AT32F421C8T7 Manuals
Manuals and User Guides for ARTERY AT32F421C8T7. We have
2
ARTERY AT32F421C8T7 manuals available for free PDF download: Reference Manual
ARTERY AT32F421C8T7 Reference Manual (337 pages)
ARM-based 32-bit Cortex-M4 MCU with 16 to 64 KB Flash, sLib, 10 timers, ADC, 7 communication interfaces
Brand:
ARTERY
| Category:
Microcontrollers
| Size: 5 MB
Table of Contents
Table of Contents
2
System Architecture
25
Figure 1-1 AT32F421 Series Microcontrollers System Architecture
26
System Overview
27
ARM Cortex
27
TM -M4 Processor
27
Bit Band
27
Figure 1-2 Internal Block Diagram of Cortex ® -M4
27
Figure 1-3 Comparison between Bit-Band Region and Its Alias Region: Image a
27
Figure 1-4 Comparison between Bit-Band Region and Its Alias Region: Image B
28
Table 1-1 Bit-Band Address Mapping in SRAM
28
Interrupt and Exception Vectors
29
Table 1-2 Bit-Band Address Mapping in the Peripheral Area
29
Table 1-3 AT32F421 Series Vector Table
29
System Tick (Systick)
31
Reset
31
Figure 1-5 Reset Process
31
Figure 1-6 Example of MSP and PC Initialization
32
List of Abbreviations for Registers
33
Device Characteristics Information
33
Flash Memory Size Register
33
Device Electronic Signature
33
Table 1-4 List of Abbreviations for Registers
33
Table 1-5 List of Abbreviations for Registers
33
Memory Resources
34
Internal Memory Address Map
34
Figure 2-1AT32F421 Address Mapping
34
Flash Memory
35
SRAM Memory
35
Table 2-1 Flash Memory Organization (64 KB)
35
Table 2-2 Flash Memory Organization (32 KB)
35
Table 2-3 Flash Memory Organization (16 KB)
35
Peripheral Address Map
36
Table 2-4 Peripheral Boundary Address
36
Power Control (PWC)
39
Introduction
39
Main Features
39
Figure 3-1 Block Diagram of each Power Supply
39
Por/Lvr
40
Power Voltage Monitor (PVM)
40
Figure 3-2 Power-On Reset/Low Voltage Reset Waveform
40
Power Domain
41
Power Saving Modes
41
Figure 3-3 PVM Threshold and Output
41
PWC Registers
43
Power Control Register (PWC_CTRL)
43
Table 3-1 PW Register Map and Reset Values
43
Power Control/Status Register (PWC_CTRLSTS)
44
Power Control Register 2 (PWC_CTRL2)
44
Clock and Reset Manage (CRM)
45
Clock
45
Clock Sources
45
Figure 4-1 AT32F421 Clock Tree
45
System Clock
46
Peripheral Clock
46
Clock Fail Detector
47
Auto Step-By-Step System Clock Switch
47
Internal Clock Output
47
Interrupts
47
Reset
47
System Reset
47
Battery Powered Domain Reset
48
CRM Registers
48
Figure 4-2 System Reset Circuit
48
Table 4-1 CRM Register Map and Reset Values
48
Clock Control Register (CRM_CTRL)
49
Clock Configuration Register (CRM_CFG)
50
Clock Interrupt Register (CRM_CLK INT)
51
APB2 Peripheral Reset Register (CRM_APB2RST)
52
APB1 Peripheral Reset Register1 (CRM_APB1RST)
53
AHB Peripheral Clock Enable Register (CRM_AHBEN)
53
APB2 Peripheral Clock Enable Register (CRM_APB2EN)
54
APB1 Peripheral Clock Enable Register (CRM_APB1EN)
55
Battery Powered Domain Control Register (CRM_BPDC)
56
Control/Status Register (CRM_CTRLSTS)
56
AHB Peripheral Reset Register (CRM_AHBRST)
57
PLL Configuration Register (CRM_PLL)
57
Additional Register (CRM_MISC1)
58
Additional Register (CRM_MISC2)
59
Embedded Flash Memory Controller (FLASH)
60
FLASH Introduction
60
Table 5-1 Flash Memory Architecture(64 K)
60
Table 5-2 Flash Memory Architecture(32 K)
60
Table 5-3 Flash Memory Architecture(16 K)
60
Table 5-4 User System Data Area
61
Flash Memory Operation
62
Unlock/Lock
62
Erase Operation
62
Figure 5-1 Flash Memory Sector Erase Process
63
Programming Operation
64
Figure 5-2 Flash Memory Mass Erase Process
64
Read Operation
65
Main Flash Memory Extension Area
65
Figure 5-3 Flash Memory Programming Process
65
User System Data Area
66
Unlock/Lock
66
Erase Operation
66
Figure 5-4 System Data Area Erase Process
67
Programming Operation
68
Figure 5-5 System Data Area Programming Process
68
Read Operation
69
Flash Memory Protection
69
Access Protection
69
Table 5-5 Flash Memory Access Limit
69
Erase/Program Protection
70
Read Access
70
Special Functions
70
Security Library Settings
70
Boot Memory Used as Memory Extension Area
71
CRC Verify
72
Flash Memory Registers
72
Table 5-6 Flash Memory Interface-Register Map and Reset Value
72
Flash Performance Select Register (FLASH_PSR)
73
Flash Unlock Register (FLASH_UNLOCK)
73
Flash User System Data Unlock Register (FLASH_USD_UNLOCK)
73
Flash Status Register (FLASH_STS)
74
Flash Control Register (FLASH_CTRL)
75
Flash Address Register (FLASH_ADDR)
76
User System Data Register (FLASH_USD)
76
Erase/Program Protection Status Register (FLASH_EPPS)
76
Flash Security Library Status Register 0 (SLIB_STS0)
77
Flash Security Library Status Register1 (SLIB_STS1)
77
Security Library Password Clear Register (SLIB_PWD_CLR)
78
Security Library Additional Status Register (SLIB_MISC_STS)
78
Flash CRC Address Register (FLASH_CRC_ARR)
78
Flash CRC Control Register (FLASH_CRC_CTRL)
79
Flash CRC Check Result Register (FLASH_CRC_CHKR)
79
Security Library Password Setting Register (SLIB_SET_PWD)
79
Security Library Address Setting Register (SLIB_SET_RANGE)
79
Boot Memory Mode Setting Register (BTM_MODE_SET)
81
Security Library Unlock Register (FLASH_UNLOCK)
81
General-Purpose I/Os (Gpios)
82
Introduction
82
Functional Overview
82
GPIO Structure
82
GPIO Reset Status
82
Figure 6-1 GPIO Basic Structure
82
General-Purpose Input Configuration
83
Analog Input/Output Configuration
83
General-Purpose Output Configuration
83
GPIO Port Protection
83
IOMUX Structure
84
Multiplexed Function Input Configuration
84
Figure 6-2 IOMUX Structure
84
IOMUX Function Input/Output
85
Table 6-1 Multiplexed Function Configuration for Port a Using GPIO_A MUX* Register
85
Table 6-2 Multiplexed Function Configuration for Port B Using GPIO_B MUX* Register
86
Table 6-3 Multiplexed Function Configuration for Port F Using GPIO_F MUX* Register
86
Peripheral Multiplexed Function Configuration
87
IOMUX Map Priority
87
External Interrupt/Wake-Up Lines
87
GPIO Registers
87
Table 6-4 Hardware Preemption
87
Table 6-5 GPIO Register Map and Reset Values
87
GPIO Configuration Register (Gpiox_Cfgr) (X=A
88
GPIO Input Mode Register (Gpiox_Omode) (X=A
88
GPIO Drive Capability Register (Gpiox_Odrvr) (X=A..h
88
GPIO Pull-Up/Pull-Down Register (Gpiox_Pull) (X=A..h
88
GPIO Input Data Register (Gpiox_Idt) (X=A
89
GPIO Output Data Register (Gpiox_Odt) (X= a
89
GPIO Set/Clear Register (Gpiox_Scr) (X=A
89
GPIO Write Protection Register (Gpiox_Wpr) (X=A
89
GPIO Multiplexed Function Low Register (Gpiox_Muxl) (X=A
90
GPIO Multiplexed Function High Register (Gpiox_Muxh) (X=A
90
GPIO Bit Clear Register (Gpiox_Clr) (X=A
90
GPIO Huge Current Control Register (Gpiox_Hdrv) (X=A
90
System Configuration Controller (SCFG)
91
Introduction
91
SCFG Registers
91
SCFG Configuration Register1 (SCFG_CFG1)
91
SCFG External Interrupt Configuration Register1 (SCFG_ EXINTC1)
92
SCFG External Interrupt Configuration Register2 (SCFG_ EXINTC2)
93
SCFG External Interrupt Configuration Register3 (SCFG_ EXINTC3)
93
SCFG External Interrupt Configuration Register4 (SCFG_ EXINTC4)
94
External Interrupt/Event Controller (EXINT)
95
EXINT Introduction
95
Function Overview and Configuration Procedure
95
Figure 8-1 External Interrupt/Event Controller Block Diagram
95
EXINT Registers
96
Interrupt Enable Register (EXINT_INTEN)
96
Event Enable Register (EXINT_EVTEN)
96
Polarity Configuration Register1 (EXINT_ POLCFG1)
96
Table 8-1 External Interrupt/Event Controller Register Map and Reset Value
96
Polarity Configuration Register2 (EXINT_ POLCFG2)
97
Software Trigger Register (EXINT_ SWTRG)
97
Interrupt Status Register (EXINT_ INTSTS)
97
DMA Controller (DMA)
98
Introduction
98
Main Features
98
Functional Overview
98
DMA Configuration
98
Figure 9-1 DMA Block Diagram
98
Handshake Mechanism
99
Arbiter
99
Figure 9-2 Re-Arbitrate after Request/Acknowledge
99
Programmable Data Transfer Width
100
Figure 9-3 PWIDTH: Byte, MWIDTH: Half-Word
100
Figure 9-4 PWIDTH: Half-Word, MWIDTH: Word
100
Figure 9-5 PWIDTH: Word, MWIDTH: Byte
100
Errors
101
Interrupts
101
Fixed DMA Request Mapping
101
Table 9-1 DMA Error Event
101
Table 9-2 DMA Interrupt Requests
101
Table 9-3 DMA Requests for each Channel
101
DMA Registers
102
Table 9-4 DMA Register Map and Reset Value
102
DMA Interrupt Status Register (DMA_STS)
103
DMA Interrupt Flag Clear Register (DMA_CLR)
104
DMA Channel-X Configuration Register (Dma_Cxctrl)
105
DMA Channel-X Number of Data Register (Dma_Cxdtcnt) (X = 1
106
DMA Channel-X Peripheral Address Register (Dma_Cxpaddr) (X = 1
106
DMA Channel-X Memory Address Register (Dma_Cxmaddr) (X = 1
106
CRC Calculation Unit (CRC)
107
CRC Introduction
107
CRC Registers
107
Data Register (CRC_DT)
107
Common Data Register (CRC_CDT)
107
Table 10-1 CRC Register Map and Reset Value
107
Control Register (CRC_CTRL)
108
Initialization Register (CRC_IDT)
108
C Interface
109
I 2 C Introduction
109
I 2 C Main Features
109
I 2 C Functional Overview
109
Figure 11-1 I C Bus Protocol
109
I 2 C Interface
110
Figure 11-2 I C Function Block Diagram
110
C Slave Communication Flow
111
Figure 11-3 Transfer Sequence of Slave Transmitter
112
Figure 11-4 Transfer Sequence of Slave Receiver
113
C Master Communication Flow
114
Figure 11-5 Transfer Sequence of Master Transmitter
114
Figure 11-6 Transfer Sequence of Master Receiver
116
Figure 11-7 Transfer Sequence of Master Receiver When N>2
117
Figure 11-8 Transfer Sequence of Master Receiver When N=2
118
Figure 11-9 Transfer Sequence of Master Receiver When N=1
119
Data Transfer Using DMA
120
Smbus
121
C Interrupt Requests
122
C Debug Mode
123
I 2 C Registers
123
Control Register1 (I2C_CTRL1)
123
Table 11-1 I 2 C Register Map and Reset Values
123
Control Register2 (I2C_CTRL2)
124
Own Address Register1 (I2C_OADDR1)
125
Own Address Register2 (I2C_OADDR2)
125
Data Register (I2C_DT)
126
Status Register1 (I2C_STS1)
126
Status Register2 (I2C_STS2)
128
Clock Control Register (I2C_ CLKCTRL)
129
Clock Rise Time Register (I2C_TMRISE)
129
Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
130
USART Introduction
130
Figure 12-1 USART Block Diagram
130
Full-Duplex/Half-Duplex Selector
132
Mode Selector
132
Introduction
132
Configuration Procedure
132
Figure 12-2 BFF and FERR Detection in LIN Mode
133
Figure 12-3 Smartcard Frame Format
133
Figure 12-4 Irda DATA(3/16) - Normal Mode
134
Figure 12-5 Hardware Flow Control
134
Figure 12-6 Mute Mode Using Idle Line or Address Mark Detection
135
Figure 12-7 8-Bit Format USART Synchronous Mode
135
USART Frame Format and Configuration
136
Figure 12-8 Word Length
136
DMA Transfer Introduction
137
Transmission Using DMA
137
Reception Using DMA
137
Figure 12-9 Stop Bit Configuration
137
Baud Rate Generation
138
Introduction
138
Configuration
138
Table 12-1 Baud Rate Calculation Error
138
Transmitter
139
Transmitter Introduction
139
Transmitter Configuration
139
Figure 12-10 TDC/TDBE Behavior When Transmitting
139
Receiver
140
Receiver Introduction
140
Receiver Configuration
140
Start Bit and Noise Detection
141
Table 12-2 Data Sampling over Start Bit and Noise Detection
141
Table 12-3 Data Sampling over Valid Data and Noise Detection
141
Tx/Rx Swap
142
Interrupt Requests
142
Figure 12-11 Data Sampling for Noise Detection
142
Figure 12-12 Tx/Rx Swap
142
Table 12-4 USART Interrupt Request
142
I/O Pin Control
143
USART Registers
143
Figure 12-13 USART Interrupt Map Diagram
143
Table 12-5 USART Register Map and Reset Value
143
Status Register (USART_STS)
144
Data Register (USART_DT)
145
Baud Rate Register (USART_BAUDR)
145
Control Register1 (USART_CTRL1)
145
Control Register2 (USART_CTRL2)
146
Control Register3 (USART_CTRL3)
147
Guard Time and Divider Register (USART_GDIV)
148
Serial Peripheral Interface (SPI)
149
SPI Introduction
149
Functional Overview
149
SPI Description
149
Figure 13-1 SPI Block Diagram
149
Full-Duplex/Half-Duplex Selector
150
Figure 13-2 SPI Two-Wire Unidirectional Full-Duplex Connection
150
Figure 13-3 Single-Wire Unidirectional Receive Only in SPI Master Mode
150
Figure 13-4 Single-Wire Unidirectional Receive Only in SPI Slave Mode
151
Figure 13-5 Single-Wire Bidirectional Half-Duplex Mode
151
Chip Select Controller
152
SPI_SCK Controller
152
Crc
152
DMA Transfer
153
Transmitter
154
Receiver
154
Motorola Mode
155
Figure 13-6 Master Full-Duplex Communications
155
Figure 13-7 Slave Full-Duplex Communications
156
Figure 13-8 Slave Full-Duplex Communications
156
Figure 13-9 Slave Half-Duplex Receive
156
Interrupts
157
Figure 13-10 Slave Half-Duplex Transmit
157
Figure 13-11 Master Half-Duplex Receive
157
Figure 13-12 SPI Interrupts
157
IO Pin Control
158
Precautions
158
I2S Functional Description
158
S Introduction
158
Figure 13-13 I 2 S Block Diagram
158
Operation Mode Selector
159
Figure 13-14 I 2 S Slave Device Transmission
159
Figure 13-15 I 2 S Slave Device Reception
159
Audio Protocol Selector
160
Figure 13-16 I 2 S Master Device Transmission
160
Figure 13-17 I 2 S Master Device Reception
160
I2S_CLK Controller
161
Figure 13-18 CK & MCK Source in Master Mode
162
Table 13-1 Audio Frequency Precision Using System Clock
162
DMA Transfer
163
Transmitter/Receiver
164
I2S Communication Timings
165
Interrupts
165
IO Pin Control
165
Figure 13-19 Audio Standard Timings
165
Figure 13-20 I 2 S Interrupts
165
SPI Registers
166
SPI Control Register1 (SPI_CTRL1)
166
Mode
166
Table 13-2 SPI Register Map and Reset Value
166
SPI Control Register2 (SPI_CTRL2)
167
SPI Status Register (SPI_STS)
168
SPI Data Register (SPI_DT)
168
SPICRC Register (SPI_CPOLY)
168
Mode)
168
Spirxcrc Register (SPI_RCRC)
169
Mode)
169
Spitxcrc Register (SPI_TCRC)
169
SPI_I2S Configuration Register (SPI_I2SCTRL)
169
SPI_I2S Prescaler Register (SPI_I2SCLKP)
170
Timer
171
Table 14-1 TMR Functional Comparison
171
General-Purpose Timer (TMR6)
172
TMR6 Introduction
172
TMR6 Main Features
172
TMR6 Functional Overview
172
Count Clock
172
Counting Mode
172
Figure 14-1 Basic Timer Block Diagram
172
Figure 14-2 Counter Timing Diagram, CK_INT Divided by 1
172
Debug Mode
173
Figure 14-3 Counter Structure
173
Figure 14-4 Overflow Event When PRBEN=0
173
Figure 14-5 Overflow Event When PRBEN=1
173
Figure 14-6 Counter Timing Diagram, Internal Clock Divided by 4
173
TMR6 Registers
174
Table 14-2 TMR6 Register Map and Reset Value
174
TMR6 Control Register1 (Tmrx_Ctrl1)
175
TMR6 Control Register2 (Tmrx_Ctrl2)
175
TMR6 Dma/Interrupt Enable Register (Tmrx_Iden)
175
TMR6 Interrupt Status Register (Tmrx_Ists)
176
TMR6 Software Event Register (Tmrx_Swevt)
176
TMR6 Counter Value (Tmrx_Cval)
176
TMR6 Division (Tmrx_Div)
176
TMR6 Period Register (Tmrx_Pr)
176
General-Purpose Timer (TMR3)
177
TMR3 Introduction
177
TMR3 Main Features
177
TMR3 Functional Overview
177
Count Clock
177
Figure 14-7 Block Diagram of General-Purpose Timer
177
Figure 14-8 Count Clock Block Diagram
178
Figure 14-9 Use CK_INT to Drive Counter, with Tmrx_Div=0X0 and Tmrx_Pr=0X16
178
Figure 14-10 Block Diagram of External Clock Mode a
179
Figure 14-11 Counting in External Clock Mode A, with Pr=0X32 and DIV=0X0
179
Figure 14-12 Block Diagram in External Clock Mode B
179
Figure 14-13 Counting in External Clock Mode B, with Pr=0X32 and DIV=0X0
180
Figure 14-14 Counter Timing with Prescaler Value Changing from 1 to 4
180
Table 14-3 TMR3 Internal Trigger Connection
180
Counting Mode
181
Figure 14-15 Counter Structure
181
Figure 14-16 Overflow Event When PRBEN=0
181
Figure 14-17 Overflow Event When PRBEN=1
182
Figure 14-18 Counter Timing Diagram, Internal Clock Divided by 4
182
Figure 14-19 Counter Timing Diagram, Internal Clock Divided by 1, Tmrx_Pr=0X32
183
Figure 14-20 Encoder Mode Structure
183
TMR Input Function
184
Figure 14-21 Example of Counter Behavior in Encoder Interface Mode (Encoder Mode C)
184
Table 14-4 Counting Direction Versus Encoder Signals
184
Figure 14-22 Input/Output Channel 1 Main Circuit
185
Figure 14-23 Channel 1 Input Stage
185
TMR Output Function
186
Figure 14-24 PWM Input Mode Configuration
186
Figure 14-25 PWM Input Mode
186
Figure 14-26 Capture/Compare Channel Output Stage (Channel 1 to 4)
187
Figure 14-27 C1ORAW Toggles When Counter Value Matches the C1DT Value
188
Figure 14-28 Upcounting Mode and PWM Mode a
188
Figure 14-29 Up/Down Counting Mode and PWM Mode a
188
Figure 14-30 One-Pulse Mode
189
Figure 14-31 Clearing Cxoraw(PWM Mode A) by EXT Input
189
TMR Synchronization
190
Figure 14-32 Example of Reset Mode
190
Figure 14-33 Example of Suspend Mode
190
Figure 14-34 Example of Trigger Mode
190
Figure 14-35 Master/Slave Timer Connection
191
Figure 14-36 Using Master Timer to Start Slave Timer
191
Debug Mode
192
TMR3 Registers
192
Figure 14-37 Starting Master and Slave Timers Synchronously by an External Trigger
192
Table 14-5 TMR3 Register Map and Reset Value
192
Control Register1 (TMR3_CTRL1)
193
Control Register2 (TMR3_CTRL2)
194
Slave Timer Control Register (TMR3_STCTRL)
194
Dma/Interrupt Enable Register (TMR3_IDEN)
195
Interrupt Status Register (TMR3_ISTS)
196
Software Event Register (TMR3_SW EVT)
197
Channel Mode Register1 (Tmrx_Cm1)
197
Channel Mode Register2 (TMR3_CM2)
199
Channel Control Register (TMR3_CCTRL)
200
Counter Value (TMR3_CVAL)
200
Table 14-6 Standard Cxout Channel Output Control Bit
200
Division Value (TMR3_DIV)
201
Period Register (TMR3_PR)
201
Channel 1 Data Register (TMR3_C1DT)
201
Channel 2 Data Register (TMR3_C2DT)
201
Channel 3 Data Register (TMR3_C3DT)
201
Channel 4 Data Register (TMR3_C4DT)
202
DMA Control Register (TMR3_DMACTRL)
202
DMA Data Register (TMR3_DMADT)
202
General-Purpose Timer (TMR14)
203
TMR14 Introduction
203
TMR14 Main Features
203
TMR14 Functional Overview
203
Count Clock
203
Figure 14-38 Block Diagram of General-Purpose TMR14
203
Figure 14-39 Count Clock
203
Figure 14-40 Use CK_INT to Drive Counter, with Tmrx_Div=0X0 and Tmrx_Pr=0X16
203
Counting Mode
204
Figure 14-41 Counter Timing with Prescaler Value Changing from 1 to 4
204
Figure 14-42 Counter Structure
204
TMR Input Function
205
Figure 14-43 Overflow Event When PRBEN=0
205
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ARTERY AT32F421C8T7 Reference Manual (307 pages)
Brand:
ARTERY
| Category:
Control Unit
| Size: 4 MB
Table of Contents
Table of Contents
2
System Architecture
24
Figure 1-1 AT32F421 Series Microcontrollers System Architecture
25
System Overview
26
ARM Cortex
26
TM -M4 Processor
26
Bit Band
26
Figure 1-2 Internal Block Diagram of Cortex ® -M4
26
Figure 1-3 Comparison between Bit-Band Region and Its Alias Region: Image a
26
Figure 1-4 Comparison between Bit-Band Region and Its Alias Region: Image B
27
Table 1-1 Bit-Band Address Mapping in SRAM
27
Interrupt and Exception Vectors
28
Table 1-2 Bit-Band Address Mapping in the Peripheral Area
28
Table 1-3 AT32F421 Series Vector Table
28
System Tick (Systick)
30
Reset
30
Figure 1-5 Reset Process
30
Figure 1-6 Example of MSP and PC Initialization
31
List of Abbreviations for Registers
32
Device Characteristics Information
32
Flash Memory Size Register
32
Device Electronic Signature
32
Table 1-4 List of Abbreviations for Registers
32
Table 1-5 List of Abbreviations for Registers
32
Memory Resources
33
Internal Memory Address Map
33
Figure 2-1AT32F421 Address Mapping
33
Flash Memory
34
SRAM Memory
34
Table 2-1 Flash Memory Organization (64 KB)
34
Table 2-2 Flash Memory Organization (32 KB)
34
Table 2-3 Flash Memory Organization (16 KB)
34
Peripheral Address Map
35
Table 2-4 Peripheral Boundary Address
35
Power Control (PWC)
38
Introduction
38
Main Features
38
Figure 3-1 Block Diagram of each Power Supply
38
Por/Lvr
39
Power Voltage Monitor (PVM)
39
Figure 3-2 Power-On Reset/Low Voltage Reset Waveform
39
Power Domain
40
Power Saving Modes
40
Figure 3-3 PVM Threshold and Output
40
PWC Registers
42
Power Control Register (PWC_CTRL)
42
Table 3-1 PW Register Map and Reset Values
42
Power Control/Status Register (PWC_CTRLSTS)
43
Power Control Register 2 (PWC_CTRL2)
43
Clock and Reset Manage (CRM)
44
Clock
44
Clock Sources
44
Figure 4-1 AT32F421 Clock Tree
44
System Clock
45
Peripheral Clock
45
Clock Fail Detector
46
Auto Step-By-Step System Clock Switch
46
Internal Clock Output
46
Interrupts
46
Reset
46
System Reset
46
Battery Powered Domain Reset
47
CRM Registers
47
Figure 4-2 System Reset Circuit
47
Table 4-1 CRM Register Map and Reset Values
47
Clock Control Register (CRM_CTRL)
48
Clock Configuration Register (CRM_CFG)
49
Clock Interrupt Register (CRM_CLKINT )
50
APB2 Peripheral Reset Register (CRM_APB2RST)
51
APB1 Peripheral Reset Register1 (CRM_APB1RST)
52
AHB Peripheral Clock Enable Register (CRM_AHBEN)
53
APB2 Peripheral Clock Enable Register (CRM_APB2EN)
54
APB1 Peripheral Clock Enable Register (CRM_APB1EN)
55
Battery Powered Domain Control Register (CRM_BPDC)
56
Control/Status Register (CRM_CTRLSTS)
56
AHB Peripheral Reset Register (CRM_AHBRST)
57
PLL Configuration Register (CRM_PLL)
58
Additional Register (CRM_MISC1)
58
Additional Register (CRM_MISC2)
59
Flash Memory Controller (FLASH)
60
FLASH Introduction
60
Table 5-1 Flash Memory Architecture(64 K)
60
Table 5-2 Flash Memory Architecture(32 K)
60
Table 5-3 Flash Memory Architecture(16 K)
60
Table 5-4 User System Data Area
61
Flash Memory Operation
62
Unlock/Lock
62
Erase Operation
62
Figure 5-1 Flash Memory Page Erase Process
63
Programming Operation
64
Figure 5-2 Flash Memory Mass Erase Process
64
Read Operation
65
Main Flash Memory Extension Area
65
User System Data Area
65
Unlock/Lock
65
Figure 5-3 Flash Memory Programming Process
65
Erase Operation
66
Figure 5-4 System Data Area Erase Process
66
Programming Operation
67
Figure 5-5 System Data Area Programming Process
67
Read Operation
68
Flash Memory Protection
68
Access Protection
68
Table 5-5 Flash Memory Access Limit
68
Erase/Program Protection
69
Special Functions
69
Security Library Settings
69
Bootloader Code Area Used as Flash Memory Extension
70
CRC Verify
70
Flash Memory Registers
71
Flash Performance Select Register (FLASH_PSR)
71
Table 5-6 Flash Memory Interface-Register Map and Reset Value
71
Flash Unlock Register (FLASH_UNLOCK)
72
Flash User System Data Unlock Register (FLASH_USD_UNLOCK)
72
Flash Status Register (FLASH_STS)
72
Flash Control Register (FLASH_CTRL)
73
Flash Address Register (FLASH_ADDR)
74
User System Data Register (FLASH_USD)
74
Erase/Program Protection Status Register (FLASH_EPPS)
74
Flash Security Library Status Register0 (SLIB_STS0)
75
Flash Security Library Status Register1 (SLIB_STS1)
75
Security Library Password Clear Register (SLIB_PWD_CLR)
75
Security Library Additional Status Register (SLIB_MISC_STS)
76
Flash CRC Address Register (FLASH_CRC_ARR)
76
Flash CRC Control Register (FLASH_CRC_CTRL)
76
Flash CRC Check Result Register (FLASH_CRC_CHKR)
76
Security Library Password Setting Register (SLIB_SET_PWD)
77
Security Library Address Setting Register (SLIB_SET_RANGE)
77
Flash Extension Memory Security Library Setting Register (EM_SLIB_SET)
78
Boot Mode Setting Register (BTM_MODE_SET)
78
Security Library Unlock Register (FLASH_UNLOCK)
78
General-Purpose I/Os (Gpios)
79
Introduction
79
Functional Overview
79
GPIO Structure
79
GPIO Reset Status
79
Figure 6-1 GPIO Basic Structure
79
General-Purpose Input Configuration
80
Analog Input/Output Configuration
80
General-Purpose Output Configuration
80
GPIO Port Protection
80
IOMUX Structure
81
Multiplexed Function Input Configuration
81
Figure 6-2 IOMUX Structure
81
IOMUX Function Input/Output
82
Table 6-1 Multiplexed Function Configuration for Port a Using GPIO_A MUX* Register
82
Table 6-2 Multiplexed Function Configuration for Port B Using GPIO_B MUX* Register
83
Table 6-3 Multiplexed Function Configuration for Port F Using GPIO_F MUX* Register
83
Peripheral Multiplexed Function Configuration
84
IOMUX Map Priority
84
External Interrupt/Wake-Up Lines
84
GPIO Registers
84
Table 6-4 Hardware Preemption
84
Table 6-5 GPIO Register Map and Reset Values
84
GPIO Configuration Register (Gpiox_Cfgr) (X=A
85
GPIO Input Mode Register (Gpiox_Omode) (X=A
85
GPIO Drive Capability Register (Gpiox_Odrvr) (X=A..h
85
GPIO Pull-Up/Pull-Down Register (Gpiox_Pull) (X=A..h
85
GPIO Input Data Register (Gpiox_Idt) (X=A
86
GPIO Output Data Register (Gpiox_Odt) (X= a
86
GPIO Set/Clear Register (Gpiox_Scr) (X=A
86
GPIO Write Protection Register (Gpiox_Wpr) (X=A
86
GPIO Multiplexed Function Low Register (Gpiox_Muxl) (X=A
87
GPIO Multiplexed Function High Register (Gpiox_Muxh) (X=A
87
GPIO Bit Clear Register (Gpiox_Clr) (X=A
87
GPIO Huge Current Control Register (Gpiox_Hdrv) (X=A
87
System Configuration Controller (SCFG)
88
Introduction
88
SCFG Registers
88
SCFG Configuration Register1 (SCFG_CFG1)
88
SCFG External Interrupt Configuration Register1 (SCFG_ EXINTC1)
89
SCFG External Interrupt Configuration Register2 (SCFG_ EXINTC2)
90
SCFG External Interrupt Configuration Register3 (SCFG_ EXINTC3)
90
SCFG External Interrupt Configuration Register4 (SCFG_ EXINTC4)
91
External Interrupt/Event Controller (EXINT)
92
EXINT Introduction
92
Function Overview and Configuration Procedure
92
Figure 8-1 External Interrupt/Event Controller Block Diagram
92
EXINT Registers
93
Interrupt Enable Register (EXINT_INTEN)
93
Event Enable Register (EXINT_EVTEN)
93
Polarity Configuration Register1 (EXINT_ POLCFG1)
93
Table 8-1 External Interrupt/Event Controller Register Map and Reset Value
93
Polarity Configuration Register2 (EXINT_ POLCFG2)
94
Software Trigger Register (EXINT_ SWTRG)
94
Interrupt Status Register (EXINT_ INTSTS)
94
DMA Controller (DMA)
95
Introduction
95
Main Features
95
Functional Overview
95
DMA Configuration
95
Figure 9-1 DMA Block Diagram
95
Handshake Mechanism
96
Arbiter
96
Figure 9-2 Re-Arbitrae after Request/Acknowledge
96
Programmable Data Transfer Width
97
Figure 9-3 PWIDTH: Byte, MWIDTH: Half-Word
97
Figure 9-4 PWIDTH: Half-Word, MWIDTH: Word
97
Figure 9-5 PWIDTH: Word, MWIDTH: Byte
97
Errors
98
Interrupts
98
Fixed DMA Request Mapping
98
Table 9-1 DMA Error Event
98
Table 9-2 DMA Interrupt Requests
98
Table 9-3 DMA Requests for each Channel
98
DMA Registers
99
Table 9-4 DMA Register Map and Reset Value
99
DMA Interrupt Status Register (DMA_STS)
100
DMA Interrupt Flag Clear Register (DMA_CLR)
101
DMA Channel-X Configuration Register (Dma_Cxctrl) (X = 1
102
DMA Channel-X Number of Data Register (Dma_Cxdtcnt)
103
DMA Channel-X Peripheral Address Register (Dma_Cxpaddr)
103
DMA Channel-X Memory Address Register (Dma_Cxmaddr)
103
CRC Calculation Unit (CRC)
104
CRC Introduction
104
CRC Registers
104
Data Register (CRC_DT)
104
Common Data Register (CRC_CDT)
104
Table 10-1 CRC Register Map and Reset Value
104
Control Register (CRC_CTRL)
105
Initialization Register (CRC_IDT)
105
C Interface
106
I 2 C Introduction
106
I 2 C Main Features
106
I 2 C Functional Overview
106
Figure 11-1 I C Bus Protocol
106
I 2 C Interface
107
Figure 11-2 I C Function Block Diagram
107
C Slave Communication Flow
108
Figure 11-3 Transfer Sequence of Slave Transmitter
109
Figure 11-4 Transfer Sequence of Slave Receiver
110
C Master Communication Flow
111
Figure 11-5 Transfer Sequence of Master Transmitter
111
Figure 11-6 Transfer Sequence of Master Receiver
113
Figure 11-7 Transfer Sequence of Master Receiver When N>2
114
Figure 11-8 Transfer Sequence of Master Receiver When N=2
115
Figure 11-9 Transfer Sequence of Master Receiver When N=1
116
Data Transfer Using DMA
117
Smbus
118
C Interrupt Requests
119
C Debug Mode
120
I 2 C Registers
120
Control Register1 (I2C_CTRL1)
120
Table 11-1 I 2 C Register Map and Reset Values
120
Control Register2 (I2C_CTRL2)
121
Own Address Register1 (I2C_OADDR1)
122
Own Address Register2 (I2C_OADDR2)
122
Data Register (I2C_DT)
123
Status Register1 (I2C_STS1)
123
Status Register2 (I2C_STS2)
125
Clock Control Register (I2C_ CLKCTRL)
126
Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
127
USART Introduction
127
Figure 12-1 USART Block Diagram
127
Full-Duplex/Half-Duplex Selector
129
Mode Selector
129
Introduction
129
Configuration Procedure
129
USART Frame Format and Configuration
130
DMA Transfer Introduction
130
Transmission Using DMA
130
Reception Using DMA
130
Baud Rate Generation
131
Introduction
131
Configuration
131
Table 12-1 Baud Rate Calculation Error
131
Transmitter
132
Transmitter Introduction
132
Transmitter Configuration
132
Receiver
132
Receiver Introduction
132
Receiver Configuration
133
Start Bit and Noise Detection
134
Tx/Rx Swap
134
Table 12-1 Data Sampling over Start Bit and Noise Detection
134
Table 12-2 Data Sampling over Valid Data and Noise Detection
134
Interrupt Requests
135
Figure 12-2 Tx/Rx Swap
135
Figure 12-3 USART Interrupt Map Diagram
135
Table 12-4 USART Interrupt Request
135
I/O Pin Control
136
USART Registers
136
Table 12-5 USART Register Map and Reset Value
136
Status Register (USART_STS)
137
Data Register (USART_DT)
138
Baud Rate Register (USART_BAUDR)
138
Control Register1 (USART_CTRL1)
138
Control Register2 (USART_CTRL2)
139
Control Register3 (USART_CTRL3)
140
Guard Time and Divider Register (USART_GDIV)
141
Serial Peripheral Interface (SPI)
142
SPI Introduction
142
Functional Overview
142
SPI Description
142
Figure 13-1 SPI Block Diagram
142
Full-Duplex/Half-Duplex Selector
143
Figure 13-2 SPI Two-Wire Unidirectional Full-Duplex Connection
143
Figure 13-3 Single-Wire Unidirectional Receive Only in SPI Master Mode
143
Figure 13-4 Single-Wire Unidirectional Receive Only in SPI Slave Mode
144
Figure 13-5 Single-Wire Bidirectional Half-Duplex Mode
144
Chip Select Controller
145
SPI_SCK Controller
145
Crc
145
DMA Transfer
146
Transmitter
147
Receiver
147
Motorola Mode
148
Figure 13-6 Master Full-Duplex Communications
148
Figure 13-7 Slave Full-Duplex Communications
149
Figure 13-8 Slave Full-Duplex Communications
149
Figure 13-9 Slave Half-Duplex Receive
149
Interrupts
150
Figure 13-10 Slave Half-Duplex Transmit
150
Figure 13-11 Master Half-Duplex Receive
150
Figure 13-12 SPI Interrupts
150
IO Pin Control
151
Precautions
151
I2S Functional Description
151
S Introduction
151
Figure 13-7 I 2 S Block Diagram
151
Operation Mode Selector
152
Figure 13-14 I S Slave Device Transmission
152
Figure 13-15 I S Slave Device Reception
152
Audio Protocol Selector
153
Figure 13-16 I 2 S Master Device Transmission
153
Figure 13-17 I 2 S Master Device Reception
153
I2S_CLK Controller
154
Figure 13-18 CK & MCK Source in Master Mode
155
Table 13-1 Audio Frequency Precision Using System Clock
155
DMA Transfer
156
Transmitter/Receiver
157
I2S Communication Timings
158
Interrupts
158
IO Pin Control
158
Figure 13-19 Audio Standard Timings
158
Figure 13-13 I 2 S Interrrupts
158
SPI Registers
159
SPI Control Register1 (SPI_CTRL1)
159
Mode
159
Table 13-2 SPI Register Map and Reset Value
159
SPI Control Register2 (SPI_CTRL2)
160
SPI Status Register (SPI_STS)
161
SPI Data Register (SPI_DT)
161
SPICRC Register (SPI_CPOLY)
161
Mode)
161
Spirxcrc Register (SPI_RCRC)
162
Mode)
162
Spitxcrc Register (SPI_TCRC)
162
SPI_I2S Configuration Register (SPI_I2SCTRL)
162
SPI_I2S Prescaler Register (SPI_I2SCLKP)
163
Timer
164
Table 14-1 TMR Functional Comparison
164
General-Purpose Timer (TMR6)
165
TMR6 Introduction
165
TMR6 Main Features
165
TMR6 Functional Overview
165
Count Clock
165
Counting Mode
165
Figure 14-1 Basic Timer Block Diagram
165
Figure 14-2 Counter Timing Diagram, CK_INT Divided by 1
165
Debug Mode
166
TMR6 Registers
166
Figure 14-3 Overflow Event When PRBEN=0
166
Figure 14-4 Overflow Event When PRBEN=1
166
Figure 14-5 Counting Timing Diagram When the Prescaler Division Is 4
166
Table 14-2 TMR6 Register Map and Reset Value
166
TMR6 Control Register1 (Tmrx_Ctrl1)
167
TMR6 Control Register2 (Tmrx_Ctrl2)
167
TMR6 Dma/Interrupt Enable Register (Tmrx_Iden)
167
TMR6 Interrupt Status Register (Tmrx_Ists)
168
TMR6 Software Event Register (Tmrx_Swevt)
168
TMR6 Counter Value (Tmrx_Cval)
168
TMR6 Division (Tmrx_Div)
168
TMR6 Period Register (Tmrx_Pr)
168
General-Purpose Timer (TMR3)
169
TMR3 Introduction
169
TMR3 Main Features
169
TMR3 Functional Overview
169
Count Clock
169
Figure 14-6 Block Diagram of General-Purpose
169
Figure 14-7 Counter Timing Diagram, CK_INT Divided by 1
169
Figure 14-8 Block Diagram of External Clock Mode a
170
Figure 14-9 Counter Timing Diagram in External Clock Mode a
170
Figure 14-10 Block Diagram of External Clock Mode B
170
Counting Mode
171
Figure 14-11 Counter Timing Diagram in External Clock Mode B
171
Figure 14-12 Counter Timing with Prescaler Value Changing from 1 to 4
171
Table 14-3 TMR6 Internal Trigger Connection
171
Figure 14-13 Overflow Event When PRBEN=0
172
Figure 14-14 Overflow Event When PRBEN=1
172
Figure 14-15 Counter Timing Diagram, Internal Clock Divided by 4
172
Figure 14-16 Counter Timing Diagram with Internal Clock Divided by 1 and Tmr3_Pr=0X32
172
TMR Input Function
173
Figure 14-17 Example of Counter Behavior in Encoder Interface Mode (Encoder Mode C)
173
Figure 14-18 Input/Output Channel 1 Main Circuit
173
Figure 14-19 Channel 1 Input Stage
173
Table 14-4 Couting Direction Versus Encoder Signals
173
TMR Output Function
174
Figure 14-20 Capture/Compare Channel Output Stage (Channel 1 to 4)
174
Figure 14-21 C1ORAW Toggles When Counter Value Matches the C1DT Value
175
Figure 14-22 Upcounting Mode and PWM Mode a
175
Figure 14-23 Up/Down Counting Mode and PWM Mode a
176
Figure 14-24 One-Pulse Mode
176
Figure 14-25 Clearing Cxoraw(PWM Mode A) by EXT Input
176
TMR Synchronization
177
Figure 14-26 Example of Reset Mode
177
Figure 14-27 Example of Suspend Mode
177
Figure 14-28 Example of Trigger Mode
177
Figure 14-29 Master/Slave Timer Connection
178
Figure 14-30 Using Master Timer to Start Slave Timer
178
Debug Mode
179
TMR3 Registers
179
Figure 14-31 Starting Master and Slave Timers Synchronously by an External Trigger
179
Table 14-5 TMR3 Register Map and Reset Value
179
Control Register1 (TMR3_CTRL1)
180
Control Register2 (TMR3_CTRL2)
181
Slave Timer Control Register (TMR3_STCTRL)
181
Dma/Interrupt Enable Register (TMR3_IDEN)
182
Interrupt Status Register (TMR3_ISTS)
183
Software Event Register (TMR3_SW EVT)
184
Channel Mode Register1 (Tmrx_Cm1)
184
Channel Mode Register2 (TMR3_CM2)
186
Channel Control Register (TMR3_CCTRL)
187
Counter Value (TMR3_CVAL)
187
Table 14-6 Standard Cxout Channel Output Control Bit
187
Division Value (TMR3_DIV)
188
Period Register (TMR3_PR)
188
Channel 1 Data Register (TMR3_C1DT)
188
Channel 2 Data Register (TMR3_C2DT)
188
Channel 3 Data Register (TMR3_C3DT)
188
Channel 4 Data Register (TMR3_C4DT)
189
DMA Control Register (TMR3_DMACTRL)
189
DMA Data Register (TMR3_DMADT)
189
General-Purpose Timer (TMR14)
190
TMR14 Introduction
190
TMR14 Main Features
190
TMR14 Functional Overview
190
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