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AT32F4212C8T
ARTERY AT32F4212C8T Manuals
Manuals and User Guides for ARTERY AT32F4212C8T. We have
1
ARTERY AT32F4212C8T manual available for free PDF download: Reference Manual
ARTERY AT32F4212C8T Reference Manual (337 pages)
ARM-based 32-bit Cortex-M4 MCU with 16 to 64 KB Flash, sLib, 10 timers, ADC, 7 communication interfaces
Brand:
ARTERY
| Category:
Microcontrollers
| Size: 5 MB
Table of Contents
Table of Contents
2
System Architecture
25
Figure 1-1 AT32F421 Series Microcontrollers System Architecture
26
System Overview
27
ARM Cortex
27
TM -M4 Processor
27
Bit Band
27
Figure 1-2 Internal Block Diagram of Cortex ® -M4
27
Figure 1-3 Comparison between Bit-Band Region and Its Alias Region: Image a
27
Figure 1-4 Comparison between Bit-Band Region and Its Alias Region: Image B
28
Table 1-1 Bit-Band Address Mapping in SRAM
28
Interrupt and Exception Vectors
29
Table 1-2 Bit-Band Address Mapping in the Peripheral Area
29
Table 1-3 AT32F421 Series Vector Table
29
System Tick (Systick)
31
Reset
31
Figure 1-5 Reset Process
31
Figure 1-6 Example of MSP and PC Initialization
32
List of Abbreviations for Registers
33
Device Characteristics Information
33
Flash Memory Size Register
33
Device Electronic Signature
33
Table 1-4 List of Abbreviations for Registers
33
Table 1-5 List of Abbreviations for Registers
33
Memory Resources
34
Internal Memory Address Map
34
Figure 2-1AT32F421 Address Mapping
34
Flash Memory
35
SRAM Memory
35
Table 2-1 Flash Memory Organization (64 KB)
35
Table 2-2 Flash Memory Organization (32 KB)
35
Table 2-3 Flash Memory Organization (16 KB)
35
Peripheral Address Map
36
Table 2-4 Peripheral Boundary Address
36
Power Control (PWC)
39
Introduction
39
Main Features
39
Figure 3-1 Block Diagram of each Power Supply
39
Por/Lvr
40
Power Voltage Monitor (PVM)
40
Figure 3-2 Power-On Reset/Low Voltage Reset Waveform
40
Power Domain
41
Power Saving Modes
41
Figure 3-3 PVM Threshold and Output
41
PWC Registers
43
Power Control Register (PWC_CTRL)
43
Table 3-1 PW Register Map and Reset Values
43
Power Control/Status Register (PWC_CTRLSTS)
44
Power Control Register 2 (PWC_CTRL2)
44
Clock and Reset Manage (CRM)
45
Clock
45
Clock Sources
45
Figure 4-1 AT32F421 Clock Tree
45
System Clock
46
Peripheral Clock
46
Clock Fail Detector
47
Auto Step-By-Step System Clock Switch
47
Internal Clock Output
47
Interrupts
47
Reset
47
System Reset
47
Battery Powered Domain Reset
48
CRM Registers
48
Figure 4-2 System Reset Circuit
48
Table 4-1 CRM Register Map and Reset Values
48
Clock Control Register (CRM_CTRL)
49
Clock Configuration Register (CRM_CFG)
50
Clock Interrupt Register (CRM_CLK INT)
51
APB2 Peripheral Reset Register (CRM_APB2RST)
52
APB1 Peripheral Reset Register1 (CRM_APB1RST)
53
AHB Peripheral Clock Enable Register (CRM_AHBEN)
53
APB2 Peripheral Clock Enable Register (CRM_APB2EN)
54
APB1 Peripheral Clock Enable Register (CRM_APB1EN)
55
Battery Powered Domain Control Register (CRM_BPDC)
56
Control/Status Register (CRM_CTRLSTS)
56
AHB Peripheral Reset Register (CRM_AHBRST)
57
PLL Configuration Register (CRM_PLL)
57
Additional Register (CRM_MISC1)
58
Additional Register (CRM_MISC2)
59
Embedded Flash Memory Controller (FLASH)
60
FLASH Introduction
60
Table 5-1 Flash Memory Architecture(64 K)
60
Table 5-2 Flash Memory Architecture(32 K)
60
Table 5-3 Flash Memory Architecture(16 K)
60
Table 5-4 User System Data Area
61
Flash Memory Operation
62
Unlock/Lock
62
Erase Operation
62
Figure 5-1 Flash Memory Sector Erase Process
63
Programming Operation
64
Figure 5-2 Flash Memory Mass Erase Process
64
Read Operation
65
Main Flash Memory Extension Area
65
Figure 5-3 Flash Memory Programming Process
65
User System Data Area
66
Unlock/Lock
66
Erase Operation
66
Figure 5-4 System Data Area Erase Process
67
Programming Operation
68
Figure 5-5 System Data Area Programming Process
68
Read Operation
69
Flash Memory Protection
69
Access Protection
69
Table 5-5 Flash Memory Access Limit
69
Erase/Program Protection
70
Read Access
70
Special Functions
70
Security Library Settings
70
Boot Memory Used as Memory Extension Area
71
CRC Verify
72
Flash Memory Registers
72
Table 5-6 Flash Memory Interface-Register Map and Reset Value
72
Flash Performance Select Register (FLASH_PSR)
73
Flash Unlock Register (FLASH_UNLOCK)
73
Flash User System Data Unlock Register (FLASH_USD_UNLOCK)
73
Flash Status Register (FLASH_STS)
74
Flash Control Register (FLASH_CTRL)
75
Flash Address Register (FLASH_ADDR)
76
User System Data Register (FLASH_USD)
76
Erase/Program Protection Status Register (FLASH_EPPS)
76
Flash Security Library Status Register 0 (SLIB_STS0)
77
Flash Security Library Status Register1 (SLIB_STS1)
77
Security Library Password Clear Register (SLIB_PWD_CLR)
78
Security Library Additional Status Register (SLIB_MISC_STS)
78
Flash CRC Address Register (FLASH_CRC_ARR)
78
Flash CRC Control Register (FLASH_CRC_CTRL)
79
Flash CRC Check Result Register (FLASH_CRC_CHKR)
79
Security Library Password Setting Register (SLIB_SET_PWD)
79
Security Library Address Setting Register (SLIB_SET_RANGE)
79
Boot Memory Mode Setting Register (BTM_MODE_SET)
81
Security Library Unlock Register (FLASH_UNLOCK)
81
General-Purpose I/Os (Gpios)
82
Introduction
82
Functional Overview
82
GPIO Structure
82
GPIO Reset Status
82
Figure 6-1 GPIO Basic Structure
82
General-Purpose Input Configuration
83
Analog Input/Output Configuration
83
General-Purpose Output Configuration
83
GPIO Port Protection
83
IOMUX Structure
84
Multiplexed Function Input Configuration
84
Figure 6-2 IOMUX Structure
84
IOMUX Function Input/Output
85
Table 6-1 Multiplexed Function Configuration for Port a Using GPIO_A MUX* Register
85
Table 6-2 Multiplexed Function Configuration for Port B Using GPIO_B MUX* Register
86
Table 6-3 Multiplexed Function Configuration for Port F Using GPIO_F MUX* Register
86
Peripheral Multiplexed Function Configuration
87
IOMUX Map Priority
87
External Interrupt/Wake-Up Lines
87
GPIO Registers
87
Table 6-4 Hardware Preemption
87
Table 6-5 GPIO Register Map and Reset Values
87
GPIO Configuration Register (Gpiox_Cfgr) (X=A
88
GPIO Input Mode Register (Gpiox_Omode) (X=A
88
GPIO Drive Capability Register (Gpiox_Odrvr) (X=A..h
88
GPIO Pull-Up/Pull-Down Register (Gpiox_Pull) (X=A..h
88
GPIO Input Data Register (Gpiox_Idt) (X=A
89
GPIO Output Data Register (Gpiox_Odt) (X= a
89
GPIO Set/Clear Register (Gpiox_Scr) (X=A
89
GPIO Write Protection Register (Gpiox_Wpr) (X=A
89
GPIO Multiplexed Function Low Register (Gpiox_Muxl) (X=A
90
GPIO Multiplexed Function High Register (Gpiox_Muxh) (X=A
90
GPIO Bit Clear Register (Gpiox_Clr) (X=A
90
GPIO Huge Current Control Register (Gpiox_Hdrv) (X=A
90
System Configuration Controller (SCFG)
91
Introduction
91
SCFG Registers
91
SCFG Configuration Register1 (SCFG_CFG1)
91
SCFG External Interrupt Configuration Register1 (SCFG_ EXINTC1)
92
SCFG External Interrupt Configuration Register2 (SCFG_ EXINTC2)
93
SCFG External Interrupt Configuration Register3 (SCFG_ EXINTC3)
93
SCFG External Interrupt Configuration Register4 (SCFG_ EXINTC4)
94
External Interrupt/Event Controller (EXINT)
95
EXINT Introduction
95
Function Overview and Configuration Procedure
95
Figure 8-1 External Interrupt/Event Controller Block Diagram
95
EXINT Registers
96
Interrupt Enable Register (EXINT_INTEN)
96
Event Enable Register (EXINT_EVTEN)
96
Polarity Configuration Register1 (EXINT_ POLCFG1)
96
Table 8-1 External Interrupt/Event Controller Register Map and Reset Value
96
Polarity Configuration Register2 (EXINT_ POLCFG2)
97
Software Trigger Register (EXINT_ SWTRG)
97
Interrupt Status Register (EXINT_ INTSTS)
97
DMA Controller (DMA)
98
Introduction
98
Main Features
98
Functional Overview
98
DMA Configuration
98
Figure 9-1 DMA Block Diagram
98
Handshake Mechanism
99
Arbiter
99
Figure 9-2 Re-Arbitrate after Request/Acknowledge
99
Programmable Data Transfer Width
100
Figure 9-3 PWIDTH: Byte, MWIDTH: Half-Word
100
Figure 9-4 PWIDTH: Half-Word, MWIDTH: Word
100
Figure 9-5 PWIDTH: Word, MWIDTH: Byte
100
Errors
101
Interrupts
101
Fixed DMA Request Mapping
101
Table 9-1 DMA Error Event
101
Table 9-2 DMA Interrupt Requests
101
Table 9-3 DMA Requests for each Channel
101
DMA Registers
102
Table 9-4 DMA Register Map and Reset Value
102
DMA Interrupt Status Register (DMA_STS)
103
DMA Interrupt Flag Clear Register (DMA_CLR)
104
DMA Channel-X Configuration Register (Dma_Cxctrl)
105
DMA Channel-X Number of Data Register (Dma_Cxdtcnt) (X = 1
106
DMA Channel-X Peripheral Address Register (Dma_Cxpaddr) (X = 1
106
DMA Channel-X Memory Address Register (Dma_Cxmaddr) (X = 1
106
CRC Calculation Unit (CRC)
107
CRC Introduction
107
CRC Registers
107
Data Register (CRC_DT)
107
Common Data Register (CRC_CDT)
107
Table 10-1 CRC Register Map and Reset Value
107
Control Register (CRC_CTRL)
108
Initialization Register (CRC_IDT)
108
C Interface
109
I 2 C Introduction
109
I 2 C Main Features
109
I 2 C Functional Overview
109
Figure 11-1 I C Bus Protocol
109
I 2 C Interface
110
Figure 11-2 I C Function Block Diagram
110
C Slave Communication Flow
111
Figure 11-3 Transfer Sequence of Slave Transmitter
112
Figure 11-4 Transfer Sequence of Slave Receiver
113
C Master Communication Flow
114
Figure 11-5 Transfer Sequence of Master Transmitter
114
Figure 11-6 Transfer Sequence of Master Receiver
116
Figure 11-7 Transfer Sequence of Master Receiver When N>2
117
Figure 11-8 Transfer Sequence of Master Receiver When N=2
118
Figure 11-9 Transfer Sequence of Master Receiver When N=1
119
Data Transfer Using DMA
120
Smbus
121
C Interrupt Requests
122
C Debug Mode
123
I 2 C Registers
123
Control Register1 (I2C_CTRL1)
123
Table 11-1 I 2 C Register Map and Reset Values
123
Control Register2 (I2C_CTRL2)
124
Own Address Register1 (I2C_OADDR1)
125
Own Address Register2 (I2C_OADDR2)
125
Data Register (I2C_DT)
126
Status Register1 (I2C_STS1)
126
Status Register2 (I2C_STS2)
128
Clock Control Register (I2C_ CLKCTRL)
129
Clock Rise Time Register (I2C_TMRISE)
129
Universal Synchronous/Asynchronous Receiver/Transmitter (USART)
130
USART Introduction
130
Figure 12-1 USART Block Diagram
130
Full-Duplex/Half-Duplex Selector
132
Mode Selector
132
Introduction
132
Configuration Procedure
132
Figure 12-2 BFF and FERR Detection in LIN Mode
133
Figure 12-3 Smartcard Frame Format
133
Figure 12-4 Irda DATA(3/16) - Normal Mode
134
Figure 12-5 Hardware Flow Control
134
Figure 12-6 Mute Mode Using Idle Line or Address Mark Detection
135
Figure 12-7 8-Bit Format USART Synchronous Mode
135
USART Frame Format and Configuration
136
Figure 12-8 Word Length
136
DMA Transfer Introduction
137
Transmission Using DMA
137
Reception Using DMA
137
Figure 12-9 Stop Bit Configuration
137
Baud Rate Generation
138
Introduction
138
Configuration
138
Table 12-1 Baud Rate Calculation Error
138
Transmitter
139
Transmitter Introduction
139
Transmitter Configuration
139
Figure 12-10 TDC/TDBE Behavior When Transmitting
139
Receiver
140
Receiver Introduction
140
Receiver Configuration
140
Start Bit and Noise Detection
141
Table 12-2 Data Sampling over Start Bit and Noise Detection
141
Table 12-3 Data Sampling over Valid Data and Noise Detection
141
Tx/Rx Swap
142
Interrupt Requests
142
Figure 12-11 Data Sampling for Noise Detection
142
Figure 12-12 Tx/Rx Swap
142
Table 12-4 USART Interrupt Request
142
I/O Pin Control
143
USART Registers
143
Figure 12-13 USART Interrupt Map Diagram
143
Table 12-5 USART Register Map and Reset Value
143
Status Register (USART_STS)
144
Data Register (USART_DT)
145
Baud Rate Register (USART_BAUDR)
145
Control Register1 (USART_CTRL1)
145
Control Register2 (USART_CTRL2)
146
Control Register3 (USART_CTRL3)
147
Guard Time and Divider Register (USART_GDIV)
148
Serial Peripheral Interface (SPI)
149
SPI Introduction
149
Functional Overview
149
SPI Description
149
Figure 13-1 SPI Block Diagram
149
Full-Duplex/Half-Duplex Selector
150
Figure 13-2 SPI Two-Wire Unidirectional Full-Duplex Connection
150
Figure 13-3 Single-Wire Unidirectional Receive Only in SPI Master Mode
150
Figure 13-4 Single-Wire Unidirectional Receive Only in SPI Slave Mode
151
Figure 13-5 Single-Wire Bidirectional Half-Duplex Mode
151
Chip Select Controller
152
SPI_SCK Controller
152
Crc
152
DMA Transfer
153
Transmitter
154
Receiver
154
Motorola Mode
155
Figure 13-6 Master Full-Duplex Communications
155
Figure 13-7 Slave Full-Duplex Communications
156
Figure 13-8 Slave Full-Duplex Communications
156
Figure 13-9 Slave Half-Duplex Receive
156
Interrupts
157
Figure 13-10 Slave Half-Duplex Transmit
157
Figure 13-11 Master Half-Duplex Receive
157
Figure 13-12 SPI Interrupts
157
IO Pin Control
158
Precautions
158
I2S Functional Description
158
S Introduction
158
Figure 13-13 I 2 S Block Diagram
158
Operation Mode Selector
159
Figure 13-14 I 2 S Slave Device Transmission
159
Figure 13-15 I 2 S Slave Device Reception
159
Audio Protocol Selector
160
Figure 13-16 I 2 S Master Device Transmission
160
Figure 13-17 I 2 S Master Device Reception
160
I2S_CLK Controller
161
Figure 13-18 CK & MCK Source in Master Mode
162
Table 13-1 Audio Frequency Precision Using System Clock
162
DMA Transfer
163
Transmitter/Receiver
164
I2S Communication Timings
165
Interrupts
165
IO Pin Control
165
Figure 13-19 Audio Standard Timings
165
Figure 13-20 I 2 S Interrupts
165
SPI Registers
166
SPI Control Register1 (SPI_CTRL1)
166
Mode
166
Table 13-2 SPI Register Map and Reset Value
166
SPI Control Register2 (SPI_CTRL2)
167
SPI Status Register (SPI_STS)
168
SPI Data Register (SPI_DT)
168
SPICRC Register (SPI_CPOLY)
168
Mode)
168
Spirxcrc Register (SPI_RCRC)
169
Mode)
169
Spitxcrc Register (SPI_TCRC)
169
SPI_I2S Configuration Register (SPI_I2SCTRL)
169
SPI_I2S Prescaler Register (SPI_I2SCLKP)
170
Timer
171
Table 14-1 TMR Functional Comparison
171
General-Purpose Timer (TMR6)
172
TMR6 Introduction
172
TMR6 Main Features
172
TMR6 Functional Overview
172
Count Clock
172
Counting Mode
172
Figure 14-1 Basic Timer Block Diagram
172
Figure 14-2 Counter Timing Diagram, CK_INT Divided by 1
172
Debug Mode
173
Figure 14-3 Counter Structure
173
Figure 14-4 Overflow Event When PRBEN=0
173
Figure 14-5 Overflow Event When PRBEN=1
173
Figure 14-6 Counter Timing Diagram, Internal Clock Divided by 4
173
TMR6 Registers
174
Table 14-2 TMR6 Register Map and Reset Value
174
TMR6 Control Register1 (Tmrx_Ctrl1)
175
TMR6 Control Register2 (Tmrx_Ctrl2)
175
TMR6 Dma/Interrupt Enable Register (Tmrx_Iden)
175
TMR6 Interrupt Status Register (Tmrx_Ists)
176
TMR6 Software Event Register (Tmrx_Swevt)
176
TMR6 Counter Value (Tmrx_Cval)
176
TMR6 Division (Tmrx_Div)
176
TMR6 Period Register (Tmrx_Pr)
176
General-Purpose Timer (TMR3)
177
TMR3 Introduction
177
TMR3 Main Features
177
TMR3 Functional Overview
177
Count Clock
177
Figure 14-7 Block Diagram of General-Purpose Timer
177
Figure 14-8 Count Clock Block Diagram
178
Figure 14-9 Use CK_INT to Drive Counter, with Tmrx_Div=0X0 and Tmrx_Pr=0X16
178
Figure 14-10 Block Diagram of External Clock Mode a
179
Figure 14-11 Counting in External Clock Mode A, with Pr=0X32 and DIV=0X0
179
Figure 14-12 Block Diagram in External Clock Mode B
179
Figure 14-13 Counting in External Clock Mode B, with Pr=0X32 and DIV=0X0
180
Figure 14-14 Counter Timing with Prescaler Value Changing from 1 to 4
180
Table 14-3 TMR3 Internal Trigger Connection
180
Counting Mode
181
Figure 14-15 Counter Structure
181
Figure 14-16 Overflow Event When PRBEN=0
181
Figure 14-17 Overflow Event When PRBEN=1
182
Figure 14-18 Counter Timing Diagram, Internal Clock Divided by 4
182
Figure 14-19 Counter Timing Diagram, Internal Clock Divided by 1, Tmrx_Pr=0X32
183
Figure 14-20 Encoder Mode Structure
183
TMR Input Function
184
Figure 14-21 Example of Counter Behavior in Encoder Interface Mode (Encoder Mode C)
184
Table 14-4 Counting Direction Versus Encoder Signals
184
Figure 14-22 Input/Output Channel 1 Main Circuit
185
Figure 14-23 Channel 1 Input Stage
185
TMR Output Function
186
Figure 14-24 PWM Input Mode Configuration
186
Figure 14-25 PWM Input Mode
186
Figure 14-26 Capture/Compare Channel Output Stage (Channel 1 to 4)
187
Figure 14-27 C1ORAW Toggles When Counter Value Matches the C1DT Value
188
Figure 14-28 Upcounting Mode and PWM Mode a
188
Figure 14-29 Up/Down Counting Mode and PWM Mode a
188
Figure 14-30 One-Pulse Mode
189
Figure 14-31 Clearing Cxoraw(PWM Mode A) by EXT Input
189
TMR Synchronization
190
Figure 14-32 Example of Reset Mode
190
Figure 14-33 Example of Suspend Mode
190
Figure 14-34 Example of Trigger Mode
190
Figure 14-35 Master/Slave Timer Connection
191
Figure 14-36 Using Master Timer to Start Slave Timer
191
Debug Mode
192
TMR3 Registers
192
Figure 14-37 Starting Master and Slave Timers Synchronously by an External Trigger
192
Table 14-5 TMR3 Register Map and Reset Value
192
Control Register1 (TMR3_CTRL1)
193
Control Register2 (TMR3_CTRL2)
194
Slave Timer Control Register (TMR3_STCTRL)
194
Dma/Interrupt Enable Register (TMR3_IDEN)
195
Interrupt Status Register (TMR3_ISTS)
196
Software Event Register (TMR3_SW EVT)
197
Channel Mode Register1 (Tmrx_Cm1)
197
Channel Mode Register2 (TMR3_CM2)
199
Channel Control Register (TMR3_CCTRL)
200
Counter Value (TMR3_CVAL)
200
Table 14-6 Standard Cxout Channel Output Control Bit
200
Division Value (TMR3_DIV)
201
Period Register (TMR3_PR)
201
Channel 1 Data Register (TMR3_C1DT)
201
Channel 2 Data Register (TMR3_C2DT)
201
Channel 3 Data Register (TMR3_C3DT)
201
Channel 4 Data Register (TMR3_C4DT)
202
DMA Control Register (TMR3_DMACTRL)
202
DMA Data Register (TMR3_DMADT)
202
General-Purpose Timer (TMR14)
203
TMR14 Introduction
203
TMR14 Main Features
203
TMR14 Functional Overview
203
Count Clock
203
Figure 14-38 Block Diagram of General-Purpose TMR14
203
Figure 14-39 Count Clock
203
Figure 14-40 Use CK_INT to Drive Counter, with Tmrx_Div=0X0 and Tmrx_Pr=0X16
203
Counting Mode
204
Figure 14-41 Counter Timing with Prescaler Value Changing from 1 to 4
204
Figure 14-42 Counter Structure
204
TMR Input Function
205
Figure 14-43 Overflow Event When PRBEN=0
205
Figure 14-44 Overflow Event When PRBEN=1
205
Figure 14-45 Input/Output Channel 1 Main Circuit
205
TMR Output Function
206
Figure 14-46 Channel 1 Input Stage
206
Figure 14-47 Capture/Compare Channel Output Stage (Channel 1)
206
Debug Mode
207
TMR14 Registers
207
Figure 14-48 C1ORAW Toggles When Counter Value Matches the C1DT Value
207
Figure 14-49 Upcounting Mode and PWM Mode a
207
Control Register1 (TMR14_CTRL1)
208
Interrupt Enable Register (TMR14_IDEN)
208
Interrupt Status Register (TMR14_ISTS)
208
Table 14-7 TMR14 Register Map and Reset Value
208
Software Event Register (TMR14_SWEVT)
209
Channel Mode Register1 (TMR14_CM1)
209
Channel Control Register (TMR14_CCTRL)
212
Counter Value (TMR14_CVAL)
212
Division Value (TMR14_DIV)
212
Period Register (TMR14_PR)
212
Channel 1 Data Register (TMR14_C1DT)
212
Table 14-8 Standard Cxout Channel Output Control Bit
212
Channel Input Remap Register (TMR14_RMP)
213
General-Purpose Timer (TMR15)
214
TMR15 Introduction
214
TMR15 Main Features
214
TMR15 Functional Overview
214
Count Clock
214
Figure 14-50 Block Diagram of General-Purpose TMR15
214
Figure 14-51 Count Clock
214
Figure 14-52 Use CK_INT to Drive Counter, with Tmrx_Div=0X0 and Tmrx_Pr=0X16
215
Figure 14-53 Block Diagram of External Clock Mode a
215
Counting Mode
216
Figure 14-54 Counting in External Clock Mode A, with Pr=0X32 and DIV=0X0
216
Figure 14-55 Counter Timing with Prescaler Value Changing from 1 to 4
216
Table 14-9 TMR15 Internal Trigger Connection
216
Figure 14-56 Counter Structure
217
Figure 14-57 Overflow Event When PRBEN=0
217
Figure 14-58 Overflow Event When PRBEN=1
217
TMR Input Function
218
Figure 14-59 OVFIF When RPR=2
218
Figure 14-60 Input/Output Channel 1 Main Circuit
218
Figure 14-61 Channel 1 Input Stage
219
TMR Output Function
220
Figure 14-62 PWM Input Mode Configuration
220
Figure 14-63 PWM Input Mode
220
Figure 14-64 Channel 1 Output Stage
220
Figure 14-65 Channel 2 Output Stage
221
Figure 14-66 C1ORAW Toggles When Counter Value Matches the C1DT Value
222
Figure 14-67 Upcounting Mode and PWM Mode a
222
Figure 14-68 One-Pulse Mode
223
TMR Brake Function
224
Figure 14-69 Complementary Output with Dead-Time Insertion
224
TMR Synchronization
225
Figure 14-70 TMR Control Output
225
Figure 14-71 Example of TMR Brake Function
225
Debug Mode
226
Figure 14-72 Example of Reset Mode
226
Figure 14-73 Example of Suspend Mode
226
Figure 14-74 Example of Trigger Mode
226
TMR15 Registers
227
Control Register1 (TMR15_CTRL1)
227
Table 14-10 TMR15 Register Map and Reset Value
227
Control Register2 (TMR15_CTRL2)
228
TMR15 Slave Timer Control Register (TMR15_STCTRL)
228
TMR15 Dma/Interrupt Enable Register (TMR15_IDEN)
229
TMR15 Interrupt Status Register (TMR15_ISTS)
230
TMR15 Software Event Register (TMR15_SW EVT)
231
TMR15 Channel Mode Register1 (TMR15_CM1)
231
TMR15 Channel Control Register (TMR15_CCTRL)
234
Table 14-11 Complementary Output Channel Cxout and Cxcout Control Bits with Brake Function
235
TMR15 Counter Value (TMR15_CVAL)
236
TMR15 Division Value (TMR15_DIV)
236
TMR15 Period Register (TMR15_PR)
236
TMR15 Repetition Period Register (TMR15_RPR)
236
TMR15 Channel 1 Data Register (TMR15_C1DT)
236
TMR15 Channel 2 Data Register (TMR15_C2DT)
236
TMR15 Brake Register (TMR15_BRK)
237
TMR15 DMA Control Register (TMR15_DMACTRL)
238
TMR15 DMA Data Register (TMR15_DMADT)
238
General-Purpose Timer (TMR16 and TMR17)
239
TMR16 and TMR17 Introduction
239
TMR16 and TMR17 Main Features
239
TMR16 and TMR17 Functional Overview
239
Count Clock
239
Figure 14-75 Block Diagram of General-Purpose TMR16 and TMR17
239
Figure 14-76 Count Clock
239
Counting Mode
240
Figure 14-77 Use CK_INT to Drive Counter, with Tmrx_Div=0X0 and Tmrx_Pr=0X16
240
Figure 14-78 Counter Structure
240
TMR Input Function
241
Figure 14-79 Overflow Event When PRBEN=0
241
Figure 14-80 Overflow Event When PRBEN=1
241
Figure 14-81 OVFIF When RPR=2
241
TMR Output Function
242
Figure 14-82 Input/Output Channel 1 Main Circuit
242
Figure 14-83 Channel 1 Input Stage
242
Figure 14-84 Channel 1 Output Stage
242
Figure 14-85 C1ORAW Toggles When Counter Value Matches the C1DT Value
244
Figure 14-86 Upcounting Mode and PWM Mode a
244
Figure 14-87 One-Pulse Mode
244
TMR Brake Function
245
Figure 14-88 Complementary Output with Dead-Time Insertion
245
Debug Mode
246
TMR16 and TMR17 Registers
246
Figure 14-89 TMR Output Control
246
Figure 14-90 Example of TMR Brake Function
246
Table 14-12 TMR16 and TMR17 Register Map and Reset Value
246
TMR16 and TMR17 Control Register1 (Tmrx_Ctrl1)
247
TMR16 and TMR17 Control Register2 (Tmrx_Ctrl2)
247
TMR16 and TMR17 Dma/Interrupt Enable Register (Tmrx_Id
248
TMR16 and TMR17 Interrupt Status Register (Tmrx_Ists)
248
TMR16 and TMR17 Software Event Register (Tmrx_Swevt)
249
TMR16 and TMR17 Channel Mode Register1 (Tmrx_Cm1)
249
TMR16 and TMR17 Channel Control Register (Tmrx_Cctrl)
252
Table 14-13 Complementary Output Channel Cxout and Cxcout Control Bits with Brake Function
252
TMR16 and TMR17 Counter Value (Tmrx_Cval)
253
TMR16 and TMR17 Division Value (Tmrx_Div)
253
TMR16 and TMR17 Period Register (Tmrx_Pr)
253
TMR16 and TMR17 Repetition Period Register (Tmrx_Rpr)
253
TMR16 and TMR17 Channel 1 Data Register (Tmrx_C1Dt)
253
TMR16 and TMR17 Brake Register (Tmrx_Brk)
254
TMR16 and TMR17 DMA Control Register (Tmrx_Dmactrl)
255
TMR16 and TMR17 DMA Data Register (Tmrx_Dmadt)
255
Advanced-Control Timers (TMR1)
256
TMR1 Introduction
256
TMR1 Main Features
256
TMR1 Functional Overview
256
Count Clock
256
Figure 14-91 Block Diagram of Advanced-Control Timer
256
Figure 14-92 Count Clock
257
Figure 14-93 Use CK_INT to Drive Counter, with Tmrx_Div=0X0 and Tmrx_Pr=0X16
257
Figure 14-94 Block Diagram of External Clock Mode a
258
Figure 14-95 Counting in External Clock Mode A, with Pr=0X32 and DIV=0X0
258
Figure 14-96 Block Diagram of External Clock Mode B
259
Figure 14-97 Counting in External Clock Mode B, with Pr=0X32 and DIV=0X0
259
Table 14-14 TMR1 Internal Trigger Connection
259
Counting Mode
260
Figure 14-98 Counter Timing with Prescaler Value Changing from 1 to 4
260
Figure 14-99 Counter Structure
260
Figure 14-100 Overflow Event When PRBEN=0
261
Figure 14-101 Overflow Event When PRBEN=1
261
Figure 14-102 Counter Timing Diagram with Internal Clock Divided by 4
261
Figure 14-103 Counter Timing Diagram with Internal Clock Divided by 1 and Tmrx_Pr=0X32
262
Figure 14-104 OVFIF in Upcounting Mode and Up/Down Counting Mode
262
Figure 14-105 Encoder Mode Structure
263
Table 14-15 Counting Direction Versus Encoder Signals
263
TMR Input Function
264
Figure 14-106 Example of Encoder Interface Mode C
264
Figure 14-107 Input/Output Channel 1 Main Circuit
264
Figure 14-108 Channel 1 Input Stage
265
TMR Output Function
266
Figure 14-109 PWM Input Mode Configuration
266
Figure 14-110 PWM Input Mode
266
Figure 14-111 Output Stage for Channel 1 to 3
266
Figure 14-112 Output Stage for Channel 4
267
Figure 14-113 C1ORAW Toggles When Counter Value Matches the C1DT Value
268
Figure 14-114 Upcounting Mode and PWM Mode a
268
Figure 14-115 Up/Down Counting Mode and PWM Mode a
268
Figure 14-116 One-Pulse Mode
269
Figure 14-117 Clearing Cxoraw(PWM Mode A) by EXT Input
269
TMR Brake Function
270
Figure 14-118 Complementary Output with Dead-Time Insertion
270
TMR Synchronization
271
Figure 14-119 TMR Output Control
271
Figure 14-120 Example of TMR Brake Function
271
Debug Mode
272
Figure 14-121 Example of Reset Mode
272
Figure 14-122 Example of Suspend Mode
272
Figure 14-123 Example of Trigger Mode
272
TMR1 Registers
273
TMR1 Control Register1 (TMR1_CTRL1)
273
Table 14-16 TMR1 Register Map and Reset Value
273
TMR1 Control Register2 (TMR1_CTRL2)
275
TMR1 Slave Timer Control Register (TMR1_STCTRL)
275
TMR1 Dma/Interrupt Enable Register (TMR1_IDEN)
276
TMR1 Interrupt Status Register (TMR1_ISTS)
278
TMR1 Software Event Register (TMR1_SWEVT)
279
TMR1 Channel Mode Register1 (TMR1_CM1)
279
TMR1 Channel Mode Register2 (TMR1_CM2)
281
TMR1 Channel Control Register (TMR1_CCTRL)
282
Table 14-17 Complementary Output Channel Cxout and Cxcout Control Bits with Brake Function
283
TMR1 Counter Value (TMR1_CVAL)
284
TMR1 Division Value (TMR1_DIV)
284
TMR1 Period Register (TMR1_PR)
284
TMR1 Repetition Period Register (TMR1_RPR)
284
TMR1 Channel 1 Data Register (TMR1_C1DT)
284
TMR1 Channel 2 Data Register (TMR1_C2DT)
284
TMR1 Channel 3 Data Register (TMR1_C3DT)
285
TMR1 Channel 4 Data Register (TMR1_C4DT)
285
TMR1 Brake Register (TMR1_BRK)
285
TMR1 DMA Control Register (TMR1_DMACTRL)
286
TMR1 DMA Data Register (TMR1_DMADT)
286
Window Watchdog Timer (WWDT)
287
WWDT Introduction
287
WWDT Main Features
287
WWDT Functional Overview
287
Figure 15-1 Window Watchdog Block Diagram
287
Debug Mode
288
WWDT Registers
288
Control Register (WWDT_CTRL)
288
Figure 15-2 Window Watchdog Timing Diagram
288
Table 15-1 Minimum and Maximum Timeout Value When PCLK1=72 Mhz
288
Table 15-2 WWDT Register Map and Reset Value
288
Configuration Register (WWDT_CFG)
289
Status Register (WWDT_STS)
289
Watchdog Timer (WDT)
290
WDT Introduction
290
WDT Main Features
290
WDT Functional Overview
290
Figure 16-1 WDT Block Diagram
290
Debug Mode
291
WDT Registers
291
Command Register (WDT_CMD)
291
Divider Register (WDT_DIV)
291
Table 16-1 WDT Timeout Period (Lick=40Khz)
291
Table 16-2 WDT Register and Reset Value
291
Reload Register (WDT_RLD)
292
Status Register (WDT_STS)
292
Enhanced Real-Time Clock (ERTC)
293
ERTC Introduction
293
ERTC Main Features
293
ERTC Functional Overview
293
ERTC Clock
293
Figure 17-1 ERTC Block Diagram
293
ERTC Initialization
294
Table 17-1 ERTC Register Configuration
294
ERTC Calibration
296
Time Stamp
296
Tamper Detection
297
Multiplexed Function Output
297
ERTC Wakeup
297
ERTC Registers
298
ERTC Time Register (ERTC
298
Table 17-2 ERTC Low-Power Mode Wakeup
298
Table 17-3 Interrupt Control Bits
298
Table 17-4 ERTC Register Map and Reset Values
298
ERTC Date Register (ERTC_DATE)
299
ERTC Control Register (ERTC_CTRL)
299
ERTC Initialization and Status Register (ERTC_STS)
300
ERTC Divider Register (ERTC_DIV)
301
ERTC Alarm Clock a Register (ERTC_ALA)
301
ERTC Write Protection Register (ERTC_WP)
302
ERTC Subsecond Register (ERTC_SBS)
302
ERTC Time Adjustment Register (ERTC_TADJ)
302
ERTC Time Stamp Time Register (ERTC_TSTM)
302
ERTC Time Stamp Date Register (ERTC_TSDT)
303
ERTC Time Stamp Subsecond Register (ERTC_TSSBS)
303
ERTC Smooth Calibration Register (ERTC_SCAL)
303
ERTC Tamper Configuration Register (ERTC_TAMP)
303
ERTC Alarm Clock a Subsecond Register (ERTC_ALASBS)
305
ERTC Battery Powered Domain Data Register (Ertc_Bprx)
305
Analog-To-Digital Converter (ADC)
306
ADC Introduction
306
ADC Main Features
306
ADC Structure
306
ADC Functional Overview
307
Channel Management
307
Figure 18-1 ADC1 Block Diagram
307
Internal Temperature Sensor
308
Internal Reference Voltage
308
ADC Operation Process
308
Power-On and Calibration
308
Figure 18-2 ADC Basic Operation Process
308
Trigger
309
Figure 18-3 ADC Power-On and Calibration
309
Table 18-1 Trigger Sources for ADC1
309
Sampling and Conversion Sequence
310
Conversion Sequence Management
310
Sequence Mode
310
Automatic Preempted Group Conversion Mode
310
Figure 18-4 Sequence Mode
310
Repetition Mode
311
Partition Mode
311
Figure 18-5 Preempted Group Auto Conversion Mode
311
Figure 18-6 Repetition Mode
311
Data Management
312
Data Alignment
312
Data Read
312
Figure 18-7 Partition Mode
312
Figure 18-8 Data Alignment
312
Voltage Monitoring
313
Status Flag and Interrupts
313
ADC Registers
313
Table 18-2 ADC Register Map and Reset Values
313
ADC Status Register (ADC_STS)
314
ADC Control Register1 (ADC_CTRL1)
314
ADC Control Register2 (ADC_CTRL2)
315
ADC Sampling Time Register 1 (ADC_SPT1)
317
ADC Sampling Time Register 2 (ADC_SPT2)
318
ADC Voltage Monitor High Threshold Register (ADC_VWHB)
320
ADC Voltage Monitor Low Threshold Register (ADC_ VWLB)
320
ADC Ordinary Sequence Register 1 (ADC_ OSQ1)
321
ADC Ordinary Sequence Register 2 (ADC_OSQ2)
321
ADC Ordinary Sequence Register 3 (ADC_OSQ3)
321
ADC Preempted Sequence Register (ADC_ PSQ)
322
ADC Preempted Data Register X (ADC_ Pdtx) (X=1
322
ADC Ordinary Data Register (ADC_ ODT)
322
Comparator (COMP)
323
COMP Introduction
323
Main Features
323
Interrupt Management
323
Figure 19-1 Block Diagram of Comparator
323
Design Tips
324
Functional Overview
324
Analog Comparator
324
Glitch Filter
325
CMP Registers
325
Figure 19-2 Glitch Filter Timing When H_PULSE_CNT=1 and L_PULSE_CNT =0
325
Figure 19-3 Glitch Filter Timing When H_PULSE_CNT=2 and L_PULSE_CNT =1
325
Table 19-1 CMP Register Map and Reset Values
325
Comparator Control and Status Register 1 (COMP_CTRLSTS)
326
Glitch Filter Enable Register (G_FILTER_EN)
327
Glitch Filter High Pulse Count (HIGH-PULSE)
327
Glitch Filter Low Pulse Count (LOW-PULSE)
328
Operational Amplifer (OPA)
329
Introduction
329
Main Features
329
Functional Description
329
Infrared Timer (IRTMR)
331
Figure 21-1 IRTMR Block Diagram
331
Debug (DEBUG)
332
Debug Introduction
332
Debug and Trace
332
I/O Pin Control
332
DEBUG Registers
332
Table 22-1 DEBUG Register Address and Reset Value
332
DEBUG Device ID (DEBUG_IDCODE)
333
DEBUG Control Register (DEBUG_CTRL)
334
Revision History
336
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