Control Other Functions; Ctrl_Halt_Startup; Ctrl_Chrg_En - Analog Devices LINEAR LT8491 Manual

LT8491
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I C REGISTER DESCRIPTIONS

CONTROL OTHER FUNCTIONS

The following registers, shown in Table 11, can be written to control various functions of the LT8491. Write access
permissions are detailed in the Data: Access Permissions section. Detailed information about each register and its
respective function follow this table.
Table 11. Summary of Other Control Registers
REGISTER NAME SIZE

CTRL_HALT_STARTUP

BYTE

CTRL_CHRG_EN

BYTE
CTRL_RESTART_CHIP BYTE
CTRL_RESET_FLAG BYTE
CTRL_UPDATE_TELEM BYTE
CTRL_HALT_STARTUP
2
I C REGISTER
ADDRESS BIT NAME
0x22 -
Related Data Sheet Sections: Startup Sequence, Data: Access Permissions
CTRL_CHRG_EN
2
I C REGISTER
ADDRESS BIT NAME
0x23 Reserved
CHRG_EN
CHRG_EN is the master on/off control bit for the charger. The battery charging, and telemetry starts after CHRG_EN
is set high and is stopped when CHRG_EN is set low. More details are as follows.
After setting CHRG_EN=1:
• The charging control logic is immediately enabled as indicated by STAT_CHARGER→CHRG_LOGIC_ON=1.
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• I C write access is immediately restricted as discussed in the Data: Access Permissions section.
• The battery charging, stage timers, and fault checking starts as shown at the top of Figure 8.
• Telemetry acquisition commences as discussed in the Telemetry: Acquisition section.
After setting CHRG_EN=0:
• The power stage of the battery charger is immediately turned off as indicated by STAT_SYSTEM→SWENO=0.
• Telemetry measurements stop as discussed in the Telemetry: Acquisition section.
• The charger status register STAT_CHARGER normally clears to 0x00. If a fault was present and not cleared before
CHRG_EN=0 then its value will be 0x80.
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2
I C REGISTER
ADDRESS DESCRIPTION
0x22 Halt failing startup CRC checking.
0x23 Enable/disable battery charging.
0x24 Restart the LT8491.
0x25 Flag that is set upon reset of the LT8491.
0x26 Write this register to measure and update telemetry registers when the charging logic is off.
BIT(S) DESCRIPTION
[7:0] Write 0x5A to halt startup when the CRC checking is failing. The STAT_SYSTEM→SYSTEM_BUSY
bits will indicate 00b when the halt sequence is complete. See Startup Sequence section for more
information. Returns 0's on reads.
BIT(S) DESCRIPTION
[7:1] Reserved
[0] Discussed below.
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