I 2 C: Chip Addressing; I 2 C: Clock Stretching; C: Data Transfer Transactions; I 2 C: Powering The Interface - Analog Devices LINEAR LT8491 Manual

OPERATION
SDA A6 - A0
SCL
S
START
CONDITION ADDRESS
from the slave, the master pulls down the SDA line during
the clock pulse to indicate receipt of the data. After the
last byte has been received the master leaves the SDA
line HIGH (NACK) and issues a STOP (P) condition to
terminate the transmission.
2
I C: Chip Addressing
The CA pin is used to select one of four 7-bit chip
addresses (A6:A0). This address is sent by the master
to identify which IC it is transferring data with. The CA
pin can be tied to ground, AV
tor divider to select the desired chip address. See the
2
HW Config: I C Chip Address section for more detailed
information.
2
I C: Clock Stretching
The charger supports clock speeds up to 100kHz for the
2
I C interface. The master is required to support I
stretching to properly communicate with this charger
(slave).
2
I

C: Data Transfer Transactions

The LT8491 supports byte-writes, byte-reads, and word-
reads using the transaction formats shown in Figure 3 to
Figure 5 respectively. Figure 3 shows the required for-
mat for writing a byte of data to the LT8491. Again, the
required chip address (A6:A0) depends on the CA pin.
A single byte of data is read from the LT8491 using the
byte-read transaction shown in Figure 4. The register
address selects the data byte that is returned. This trans-
2
action requires four I C bytes to read one byte of chip data.
1 - 7 8 9
CHIP R/W ACK
Figure 2. Data Transfer Over I
or connected to a resis-
DD
2
C clock
For more information
B7 - B0
1 - 7 8 9
DATA ACK
2
C Bus
The word-read transaction, shown in Figure 5, should be
used to read telemetry such as power, volts and amps
that is stored in 16-bit formats. The word-read transac-
tion ensures that both bytes of data are properly paired
together and can be combined into a valid word. Due
to the time latency between I
bytes from two byte-read transactions may not result in
valid 16-bit telemetry data.
Referring again to Figure 5, the register address selects
the first byte of data (DATA0) that is returned. Data from
the next higher byte address is returned in the second byte
(DATA1). When reading Word or Long Word data, note
that the least significant byte is at the lowest address loca-
tion (little-endian). B0 of the register address should typi-
cally be set to 0 since all words in the LT8491 are aligned
to even register addresses. This transaction requires five
2
I C bytes to read two bytes of chip data and must be
repeated for each subsequent word of data that is read.
2
I C: Powering the Interface
2
The I C control logic and I/O are powered from the V
pin. V is ultimately supplied from either V
DD
when the SHDN pin is high. This can be seen in the block
diagram which shows that V
INTV regulator that, in turn, supplies the LDO33 regula-
CC
tor which is finally connected to V
2
rise, I C communication is enabled after a delay of 10ms
(typical). Note that the LT8491 contains diodes from the
SDA and SCL pins to the V
diodes are normally reverse biased and have no effect on
2
the I C bus. However, when the LT8491 is unpowered, the
V pin voltage will drop and may pull down on the SDA
DD
and SCL pins, thus effecting communication on the bus.
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LT8491
B7 - B0
1 - 7 8 9
DATA ACK
CONDITION
2
C transactions, combining
IN
and EXTV
IN CC
. After SHDN and V
DD
pin (see Figure 8). These
DD
P
STOP
8491 F02
DD
or EXTV
CC
supply the
DD
Rev. 0
15