Iq Modulator - Analog Devices AN-826 Application Note

IQ MODULATOR

Modulator AC Drive Level
The I and Q inputs of the modulator should be driven
differentially. For a modulation like WiMAX OFDM with
peak-to-average ratios of 10 dB and higher, the peak drive
level should be such that there is at least a 10 dB backoff from
compression to minimize the distortions. The optimum level is
actually determined by minimizing the spectral distortion at the
modulator output while maintaining sufficient SNR.
AD9862
R1
DAC1
R2
DAC2
Figure 5. DAC to IQ Modulator Interface
The interface between the AD9862
modulator is shown in Figure 5.
Resistors R1 and R2 set the dc bias level while Resistor R
the level of the baseband I and Q voltages to the modulator.
The modulator differential input voltage can be calculated from
Equation 1 and is both a function of the Resistor R
full-scale current, I .
DAC
× × ×
2 I R
=
DAC DC
V
× +
diff
2 R R
DC L
= =
R R1 R2
DC
The ADL5373 has a fixed voltage gain. The output level of the
modulator can be set by choosing the appropriate input load
resistor. As an alternative, a larger resistor can be chosen and
the full-scale output current of the DAC can be scaled to the
desired drive level.
Optimum drive level to the ADL5373 IQ modulator for an
OFDM modulation like WiMAX is 0.650 V p-p ± 10% (see the
Finding the IQ Modulator Optimum Operating Point section
for more details). At this level, the rms power level out of the
modulator is about −12 dBm, providing an optimum trade-off
between output power level and spectral quality.
This input voltage can be obtained by using a 50 Ω R
while driving the modulator with 20 mA of full-scale current.
However, it is common to operate at a given back-off from
full scale. As an example, this optimum ac level can also be set
by choosing R for a high enough peak voltage (200 Ω for
L
1.3 V p-p, for instance) and by adjusting the DAC output
current to about 10 mA (or −6 dBFS). A dc offset then needs
R
I INPUT
L
ADL5373
Q INPUT
DAC and the ADL5373
sets
L
and the DAC
L
R
= =
L
f ( I ) g ( R )
L
DAC
resistor
L
to be applied at the connecting point of R1 and R2 to maintain
the 500 mV of dc bias level. Note that with this lower full-scale
current, the ac dynamic performance of the DAC degrades by
about 2 dB.
DC Bias Level
Resistors R1 and R2 set the dc bias level. The recommended
level of common-mode voltage is 500 mV.
A value of 50 Ω generates the required 500 mV dc bias for
20 mA of DAC full-scale current, independently of the R
Baseband Filtering
With the signal being sampled at 80 MHz (20 MHz + 4×
interpolation), the requirement for image rejection can be
defined. The sample-and-hold action of the DAC is equivalent
to a convolution of the sampled waveform by a sin(x) function
in the frequency domain.
=
V ( f )
out
Figure 3 is a good example of this sampling image shaping
effect. As a result, the highest image is usually at 1 × f
80 MHz here.
The level of these sampling images can be calculated using the
sin(x)/x function.
Calculated levels are −31.6 dBc and −37.6 dBc at 1 × f
2 × f respectively, at a sampling frequency of 80 MHz. The
S
measured levels of these images were actually not very different
from these calculated values: −33 dBc and −40 dBc for the first
and second images.
(1)
The reconstruction filter at the DAC modulator interface is
there to provide the modulator with a clean baseband signal,
free from images that fall inside the RF bandwidth by
up-conversion. Low-pass Bessel structures are ideal for their
flat in-band group delay (see Figure 8). A third-order filter with
a 3 dB cutoff frequency at 8 MHz provides 50 dB of rejection at
80 MHz, bringing the sampling images down to 80 dBc.
The details of the baseband filter are shown in Figure 6 to
Figure 8.
PORT
P1
PORT
P2
Figure 6. Baseband Filter Schematic Including Source Resistor
Rev. B | Page 5 of 16
⎛ ⎞
π
sin( fT )
⎜ ⎟
×
V ( f )
⎜ ⎟
π
sampled
⎝ fT ⎠
L6
L = 820nH
R3
R = 50Ω
C8 C9
C = 47pF C = 330pF
R4
R = 50Ω
L7
L = 820nH
and Termination Resistor
AN-826
value.
L
(2)
, or
S
and
S
PORT
P3
R5
R = 200Ω
PORT
P4