Analog Devices AN-826 Application Note page 11

Figure 17 shows the power detection error with CLPF = 1 μF
and VTG = 0.625 V.
3
2
1
0
–1
CW BPSK
QPSK 1/2 QPSK 3/4
–2
16QAM 3/4 16QAM 1/2
64QAM 2/3 64QAM 3/4
–3
–60 –55 –50 –45 –40 –35 –30 –25 –20 –15 –10 –5
INPUT POWER (dBm)
Figure 17. RMS Power Detector Detection Range and
Accuracy for CLPF = 1 μF
With VTG = 0.625 V (connecting VREF to VTG through a
resistive divider) and a smaller CFLT capacitor, similar perform-
ances can be achieved with a fast averaging ADC. In such
configuration, the RMS detector is completely insensitive to
the type of OFDM modulation applied to it. Therefore, no
calibration is required, whether a QPSK or a 64 QAM modulates
the OFDM subcarriers. Figure 18 shows the power detector
settling time for CLPF = 47 nF.
1
CH1 500mV
Figure 18. Power Detector Time Response to a WiMAX Downlink Burst
(T = 25.6 μs), CLPF = 47 nF
SYMB
0 5 10
CH1 RISE
77.93µs
M1.00ms A CH1 1.33V
T 2.97200ms
RF INPUT
10dB
4dB
2.7nH
4.7nH
1nF
Figure 19. Power Detection and Temperature Compensation of the AD8362 at 2.35 GHz
Temperature Compensation
To improve the measurement accuracy of the
temperature at 2.35 GHz, a simple temperature compensation
scheme can be used. It helps correct for the drift of the detector
intercept point of the V
transfer function tends to drop with increasing temperature,
while the slope remains quite stable. Therefore, compensating the
drift at a particular input level (for example, −15 dBm) holds up
well over the dynamic range (see Figure 20).
The compensation is simple and relies on the TMP36 precision
temperature sensor. At 25°C, the TMP36 has an output voltage
of 750 mV and a temperature coefficient of 10 mV/°C. The
positive temperature coefficient of the TMP36 can directly
compensate for the negative temperature coefficient of the
detector. The implemented circuit is given in Figure 19. (Note
that the VOUT pin of AD8362 is depicted as VDET_OUT to
avoid confusion within this figure.) The resistor ratio of R1
and R2 can be calculated so that the corrected VOUT_Comp
voltage remains steady over temperature.
The temperature drift of the AD8362 at 2.35 GHz is −0.03 dB/°.
It has been measured at a detector input power of −15 dBm.
The following equation shows how of the resistor ratio is
calculated:
Δ
−
R2
=
Δ
R1
The temperature drift of the AD8362 in dB/°C is converted to
mV/°C through multiplication by the logarithmic slope of the
detector (49.79 mV/dB at 2.35 GHz). In this application, the
drift of −0.03 dB/°C is equivalent to −1.51 mV/°C.
Figure 20 shows the measured performance over temperature
for the compensated circuit at 2.35 GHz. Note that the compen-
sation factor was chosen to optimize temperature drift in the
0°C to 85°C range. This is consistent with end equipment where
performance at low temperatures is less critical.
P = –1dBm MAX
OUT
1nF AD8362
INHI
R1 R2
VDET_OUT
4.99kΩ 33.2kΩ
VSET
INLO CLPF
47nF
VTGT VREF
VOUT_Comp
Rev. B | Page 11 of 16
= f(Pin) characteristic. The whole
DET
V P
TM
o
10 mV / C
Δ
T
= −
V
AD 8362 Drift (mV/
DET
Δ
T
5V
0.1µF
TMP36F
AN-826
AD8362 over
o
C)