The Vga And The Interface To The Iq Modulator - Analog Devices AN-826 Application Note

Lock Time
PLL lock time can be critical in the following scenarios:
•
In HFDD systems where both frequency duplex and time
duplex are used.
•
During frequency hopping used to achieve better signal
quality, to increase data security, to avoid multipath fading,
or to avoid interference.
PLL lock time can be optimized by increasing the reference or
comparison frequency, and, if necessary, by increasing the loop
bandwidth.
With the ADF4153, a reference frequency or PFD frequency up
to 32 MHz can be chosen, or the available frequency doubler
can be used to increase the PFD frequency while using a lower
frequency reference clock.
The definition of the PLL loop bandwidth is a trade-off between
the required settling time, the acceptable phase error, and the
spurs level. The larger the loop bandwidth is the faster the lock
time, at the expense of higher phase error and spurs level. But if
the lock time is not critical, using a narrow-loop bandwidth is
recommended for the reasons described in the Phase Noise
section.
Performance
In this particular characterization, the PLL has been designed
for a closed-loop bandwidth of about 20 kHz. For a 10 MHz
256 OFDM signal, the symbol duration is 25.6 μs, which
corresponds to a subcarrier spacing of 39 kHz. Therefore, the
PLL loop has voluntarily been designed slower than the symbol
duration such that most of its phase noise can be tracked and
removed by the pilot-tracking algorithm. Figure 13 shows the
PLL schematic, including the loop filter.
7 15
AV DV
DD DD
RF A
CP
6
IN
RF B
5
IN
R
V SUPPLY
SET
ADF4153
V+
F
8 REF
OUT IN
GND
MUXOUT
13 LE
12 DATA
REFERENCE
TCXO10
11
CLK
10 SDV
DD
CPGND AGND DGND
4
3
Figure 13. PLL Loop Schematic
16
V
P
R2
1.50kΩ
2
C1 C3
R1
4.70nF 2.20nF
750Ω
35.0MHz/V
C2
56.0nF
1
R
SET
5.10kΩ
14
LOCK DETECT
OUT
NOTES
1. AV ANALOG POWER SUPPLY.
DD
2. DV DIGITAL POWER SUPPLY.
DD
3. V CHARGE PUMP POWER SUPPLY.
P
9
4. AV = DV , VP ≥ DV , AV
DD DD DD
5. CONSULT MANUFACTURER'S DATA
SHEET FOR FULL DETAILS.
Figure 14 shows the closed-loop phase noise performance of
this PLL.
The VCO is a Sirenza VCO190-2350T(Y), with a tuning sensi-
tivity of 35 MHz/V typical. PLL closed-loop in-band phase
noise is −95 dBc/Hz.
The equivalent rms phase error for this design is only 0.35°rms,
equivalent to an EVM contribution of 0.6%. The contribution of
this fractional-N PLL to the overall EVM performance is given
in the Overall System Performance section.
–80
–90
–100
–110
–120
–130
–140
100
Figure 14. Closed-Loop Phase Noise Simulation at 2.35 GHz
THE VGA AND THE INTERFACE TO THE IQ
MODULATOR
Because WiMAX systems can be used for nonline-of-sight
applications, gain control of the transmitter is necessary to
adjust the output Tx level depending on the channel quality.
The ADL5330
provides close to 50 dB of gain control at 2.3 GHz, with a gain
control slope of about 60 dB/V. A positive control voltage from
0.5 V to 1.4 V is required to control the gain of the VGA. At
V = 1.4 V, a maximum gain close to 15 dB is achieved. The
GAIN
basic connections for interfacing the
VCO
with the ADL5330 are shown in Figure 15.
.
DD
Rev. B | Page 9 of 16
PHASE NOISE AT 2.35GHz
1k 10k
FREQUENCY (Hz)
is a high performance VGA, 50 Ω I/O, which
ADL5373
AN-826
100k 1M
IQ modulator