Pll Interface; Table 3-19 Pll Interface; Table 3-20 External Input Clock Requirements For Refclkn/P - AMD Vega 10 Data Book

Signal Descriptions

3.18 PLL Interface

Table 3–19 PLL Interface
Pin Name
XTALIN
XTALOUT
REFCLKN
REFCLKP
OSC_GAIN[0:2]
Note: Both the 27-MHz crystal and 100-MHz differential clock must be provided to the GPU.
Table 3–20 External Input Clock Requirements for REFCLKN/P
Symbol Parameter and test conditions
Freq
V
IH
V
IL
V
CROSS
ΔV
CROS
V
swing
T /T
fall rise
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AMD Confidential - Do not duplicate.
Type
Connect a 27-MHz parallel-resonant crystal between XTALIN and
XTALOUT as a reference clock to the GPU.
Crystal characteristics:
•
I
•
A 1-MΩ resistor must be connected between XTALIN and XTALOUT
when a crystal is used.
Capacitive loading from the package and PCB trace should be
subtracted from the C1 and C2 capacitor values.
O See above.
100 MHz differential reference clock (+/-) input for GPU PLLs,
e.g.,TMDP PLL Display PLL.
200 ps (max) cycle to cycle jitter.
I
300 ps (max) long term jitter (10,000 cycles after the trigger edge).
Non-spread.
Refer to the clock specs in
Provide a pull-up resistor to 3.3 V and a pull-down resistor to GND for
I/O
each pin on the PCB.
3.3 V
By default, install only pull-up resistors on OSC_GAIN[2:1], and install
(VDDAN_33)
only pull-down resistor on OSC_GAIN[0].
Frequency
Differential Input High Voltage
Differential Input Differential
waveform
Absolute crossing point voltage
Variation of Vcross over all rising
clock edges
Voltage Swing
Rise/Fall time
Description
ESR: < 80 Ω.
Combined frequency tolerance and stability: ±30 ppm max.
Table 3–20 (p.
Min Typ Max
100
+150
-150
+250 +550 mV
+140 mV
-0.3 0.76 1
0.6 4.0
35).
Units Notes
MHz
mV Differential waveform
mV Differential waveform
Single-ended crossing
V Single-Ended including
overshoot/undershoot
V/ns Measured from 150-mV to
150-mV differential
35
"Vega 10" Databook
56006_1.00