Page 1 ST10R272L USER’S MANUAL Release 1.0 ®...
Page 2: Table Of Contents
Table of Contents 1 INTRODUCTION ..........9 2 ARCHITECTURAL OVERVIEW .
Page 3 Table of Contents 3.2 EXTERNAL MEMORY SPACE ....... 33 3.3 CROSSING MEMORY BOUNDARIES ......34 4 CENTRAL PROCESSING UNIT .
Page 4 Table of Contents 6.1.1 Interrupt sources ........84 6.1.2 Normal interrupt processing and PEC service .
Page 5 Table of Contents 7.3 PORT 2 ..........121 7.3.1 Alternate functions of port 2 .
Page 6 Table of Contents 9.4.1 Registers ..........164 9.4.2 Defining address areas .
Page 7 Table of Contents 12.1 ASYNCHRONOUS OPERATION ......228 12.2 SYNCHRONOUS OPERATION ......231 12.3 HARDWARE ERROR DETECTION CAPABILITIES .
Page 8 Table of Contents 15.1 ASYNCHRONOUS HARDWARE RESET ..... . 259 15.2 SYNCHRONOUS HARDWARE RESET (WARM RESET) ..261 15.3 SOFTWARE RESET .
Page 9 Table of Contents 17.2 POWER DOWN MODE ........295 17.2.1Protected power down mode .
Page 10: Introduction
ST10R272L USER’S MANUAL INTRODUCTION The ST10R272L is a new member of the ST10 family designed to give high performance in applications where low-power operation is important. The low-power features of the ST10R272L include: • 3.3V operation: Half the power consumption of an equivalent 5V device (250mW at 25MHz).
Page 11: Architectural Overview
ST10R272L - ARCHITECTURAL OVERVIEW ARCHITECTURAL OVERVIEW The architecture of the ST10R272L combines the advantages of both RISC and CISC processors with an advanced peripheral subsystem. The following block diagram shows the different on-chip components and the advanced - high bandwidth - internal bus structure of the ST10R272L.
Page 12: Basic Cpu Concepts
ST10R272L - ARCHITECTURAL OVERVIEW Basic CPU concepts The main core of the CPU contains a 4-stage instruction pipeline, a MAC multiply-accumulation unit, a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Most instructions can be executed in one CPU clock cycle.
Page 13: High Instruction Bandwidth / Fast Execution
2.1.1 High instruction bandwidth / fast execution Most of the ST10R272L’s instructions can be executed in just one instruction cycle - shift and rotate instructions (irrespective of the number of bits to be shifted). Branch, multiply and divide instructions normally take more than one instruction cycle, but have also been optimized.
Page 14: Extended Bit Processing And Peripheral Control
ST10R272L - ARCHITECTURAL OVERVIEW A set of consistent flags is automatically updated in the PSW after each arithmetic, logical, shift, or movement operation. These flags cause branching on specific conditions. User-specifiable branch tests give support for signed and unsigned arithmetic. These flags are preserved automatically by the CPU on entry into an interrupt or trap routine.
Page 15: Instruction Formats
ST10 Family products, and a MAC instruction set which is used for products containing the MAC. Code compiled for the non-MAC ST10/C166 processors, will run on the ST10R272L. However, MAC instructions run on non-MAC ST10/C166 processors will be trapped because undefined opcodes are used.
Page 16: On-Chip System Resources
2.2.2 Memory areas The memory space of the ST10R272L is configured in a Von Neumann architecture which means that code memory, data memory, registers and IO ports are organized within the same linear address spaces. The entire memory space can be accessed bytewise or wordwise.
Page 17: External Bus Interface
ST10R272L - ARCHITECTURAL OVERVIEW number of register banks is only restricted by the available internal RAM space. For easy parameter passing, one register bank may overlap another. A system stack of up to 512 words stores temporary data. It is located in the on-chip RAM area, and is accessed by the CPU via the Stack Pointer (SP) register.
Page 18: System Clock Generator
Both clocks are switched off when power-down mode is entered. The on-chip PLL circuit allows operation of the ST10R272L on a low frequency external clock while still providing maximum performance. The PLL multiplies the external clock frequency by a selectable factor of 1:F and generates a CPU clock signal with 50% duty cycle.
Page 19 ST10R272L - ARCHITECTURAL OVERVIEW P0H.6 Prescaler (- 2) XTAL XTAL2 Oscillator PLL Circuit Circuit = F * f XTAL1 Factor P0H.7-5 Unlock Reset reset sleep PWRDN XP3INT Oscillator Watchdog Figure 3 PLL block diagram The table below lists all the possible selections for the on-chip clock generator. Refer to the device datasheet for the specific External Clock Input Range.
Page 20: Pll Operation
XTAL Note If the ST10R272L is required to operate on the desired CPU clock directly after reset, make sure that RSTIN remains active until the PLL has locked (ca. 1 ms). The PLL constantly synchronizes to the external clock signal. Due to the fact that the external frequency is 1/F’th of the PLL output frequency, the output frequency may be...
Page 21: Oscillator Watchdog (Owd)
ST10R272L - ARCHITECTURAL OVERVIEW 2.3.4 Oscillator watchdog (OWD) The Oscillator Watchdog provides a fail safe mechanism for the loss of the external clock, for direct drive or direct drive with prescaler clock options. The oscillator watchdog is enabled by default after reset. To disable the OWD, set bit OWDDIS of the SYSCON register. When the OWD is enabled, the PLL runs on its free-running frequency, and increments the Oscillator Watchdog counter.
Page 22: Peripheral Timing
ST10R272L - ARCHITECTURAL OVERVIEW generated by the peripherals, based on specific events which occur during their operation (e.g. operation complete, error, etc.). Specific parallel port pins interface with external hardware when an input or output function has been selected for a peripheral. During this time, the port pins are controlled by the peripheral (when used as outputs) or by the external hardware which controls the peripheral (when used as inputs).
Page 23: Reserved Bits
2.4.5 Parallel ports The ST10R272L has up to 77 I/O lines, organized into six input/output ports and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs via direction registers. The I/O ports are true bidirectional ports, which are switched to high impedance state when configured as inputs.
Page 24: General Purpose Timer (Gpt)
Watchdog Timer is reloaded. Protected bits The ST10R272L provides a special bit protection mechanism. Bits which can be modified by the on-chip hardware, cannot be unintentionally changed by software accesses to related bits (“Bit-handling and bit-protection” on page 45).
Page 25 ST10R272L - ARCHITECTURAL OVERVIEW Register Bit Name Notes S0RIC, S0EIC S0RIR, S0EIR ASC0 receive/error interrupt request flags S0CON S0REN ASC0 receiver enable flag TFR.15,14,13 Class A trap flags TFR.7, 6, 3, 2,1,0 Class B trap flags XPyIC (y=1, 3) XPyIR (y=1, 3)
Page 26: Memory Organization
Register Areas (SFRs and ESFRs), the address areas for integrated XBUS peripherals and external memory are mapped into one common address space. The ST10R272L provides a total addressable memory space of 16MBytes. This address space is arranged as 256 segments of 64KBytes each, and each segment is subdivided into four data pages of 16 KBytes each (see figure below).
Page 27 / data, but not for instructions. The ST10R272L is a ROMless device: program ROM must be in external memory. Bytes are stored at even or odd byte addresses. Words are stored in ascending memory locations with the low byte at an even byte address, followed by the high byte at the next odd byte address.
Page 28: Internal Ram And Sfr Area
Internal RAM and SFR area The ST10R272L has 1 KByte of internal RAM in the address range 00’FA00h - 00’FDFFh. It is used for variables, the register banks, and the system stack. It contains the PEC pointers (address range 00’FCE0h - 00’FCFFh) and the bit-addressable space (00’FD00h - 00’FDFFh).
Page 29 ST10R272L - MEMORY ORGANIZATION 00’FFFFh 00’FFFFh RAM/SFR 00’F000h 00’FF3Fh 00’EFFFh 00’FF20h XSSP 256 Byte SFR Area 00’EF00h Data Page 3 (reserved) 00’FE3Fh 00’FE20h 00’FE00h External 00’F000h memory Area DP-RAM 1K-Byte Data Page 2 00’FA00h 00’8000h Data Page 1 Block 1...
Page 30: System Stack
ST10R272L - MEMORY ORGANIZATION Any word- and byte-data in the internal RAM can be accessed by indirect or long 16-bit addressing modes, if the selected DPP register points to data page 3. Any word-data access is made on an even byte address. The highest possible word-data storage location in the internal RAM is 00’FDFEh.
Page 31: General Purpose Registers
(independent of the current DPP register contents). Additionally, each bit in the currently active register-bank can be accessed individually. The ST10R272L supports fast register-bank (context) switching. Multiple register-banks can physically exist within the internal RAM at the same time. However, only the register-bank selected by the Context Pointer register (CP) is active at a given time.
Page 32: Pec Source And Destination Pointers
ST10R272L - MEMORY ORGANIZATION Internal RAM Address Byte Registers Word Register <CP> + 0Ah <CP> + 08h <CP> + 06h <CP> + 04h <CP> + 02h <CP> + 00h Table 4 Mapping of general purpose registers to RAM addresses 3.1.3 PEC source and destination pointers The 16 word-locations in the internal RAM from 00’FCE0h to 00’FCFFh (just below the...
Page 33: Special Function Registers
ST10R272L - MEMORY ORGANIZATION 00’FD00 00’FCFE DSTP7 00’FCFE 00’FCFC SRCP7 00’FCE0 00’FCDE PEC source & destination Internal RAM pointers DSTP0 00’FCE2 00’F600 00’F5FE 00’FCE0 SRCP0 Figure 7 Location of the PEC pointers 3.1.4 Special function registers The functions of the CPU, the bus interface, the I/O ports and the on-chip peripherals are controlled by Special Function Registers (SFRs).
Page 34: External Memory Space
EXTR instructions. External memory space The ST10R272L uses an address space of up to 16 MByte. Only parts of this address space are occupied by internal memory areas. All addresses which are not used for on-chip RAM, registers or internal Xperipherals, may reference external memory locations through the External Bus Interface.
Page 35: Crossing Memory Boundaries
ST10R272L - MEMORY ORGANIZATION Non-segmented mode: 64KByte with A15...A0 on PORT0 or PORT1. 8-bit segmented mode: 16 MByte with A23...A16 on Port 4 and A15...A0 on PORT0 or PORT1. Each bank can be directly addressed via the address bus, while ‘Programmable Chip Select Signals’...
Page 36 ST10R272L - MEMORY ORGANIZATION Segments are contiguous blocks of 64KBytes. They are referenced via the code segment pointer CSP for code fetches, and via an explicit segment number for data accesses when overriding the standard DPP scheme. During code fetching, segments are not changed automatically, but must be switched explicitly.
Page 37: Central Processing Unit
CENTRAL PROCESSING UNIT The main core of the CPU includes a 4-stage instruction pipeline, a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Most ST10R272L instructions can be executed in one machine cycle. The MAC performs multiply-accumulate operations. It has an enhanced instruction set for 32-bit arithmetic, computation and data moves.
Page 38 Data Pg. Ptrs Figure 8 CPU block diagram The on-chip peripheral units of the ST10R272L work almost independently of the CPU, with a separate clock generator. Data and control information is interchanged between the CPU and these peripherals via Special Function Registers (SFRs). Whenever peripherals need a non-deterministic CPU action, an on-chip Interrupt Controller compares all pending peripheral service requests against each other, and prioritizes one of them.
Page 39: Instruction Pipelining
A transition into an active CPU state is forced by an interrupt (if being IDLE) or by a reset (if being in POWER DOWN mode). The IDLE, POWER DOWN and RESET states can be entered by the use of ST10R272L system control instructions. Instruction pipelining...
Page 40: Standard Branch Instruction Processing
ST10R272L - CENTRAL PROCESSING UNIT instructions. Therefore, most instructions seem to be processed in one machine cycle as soon as the pipeline has been filled (see figure below). Instruction pipelining increases the average instruction throughput over a certain period of time.
Page 41: Jump Cache Instruction Processing
ST10R272L - CENTRAL PROCESSING UNIT Injection 1 Machine Cycle FETCH BRANCH TARGET TARGET+1 TARGET+2 TARGET+3 DECODE BRANCH INJECT TARGET TARGET+1 TARGET+2 EXECUTE . . . BRANCH INJECT TARGET TARGET+1 WRITEBACK ..BRANCH INJECT TARGET time Figure 10 Standard branch instruction pipelining 4.1.3...
Page 42: Pipeline Effects
(e.g. multiple usage of buses) and prevents the pipeline from becoming noticeable to the user. However, there are some cases where the fact that the ST10R272L is a pipelined machine, requires attention by the programmer. In these cases, the delays caused by pipeline conflicts can be used by other instructions, to optimize performance.
Page 43 ST10R272L - CENTRAL PROCESSING UNIT Data Page Pointer Updating An instruction, which calculates a physical operand address via a particular DPPn (n=0 to 3) register, is not capable of using a new DPPn register value which is to be updated by an immediately preceding instruction.
Page 44 ST10R272L - CENTRAL PROCESSING UNIT external memory accesses performed by the EBC, due to the predefined priority of external memory accesses: Write Data Fetch Code Read Data Controlling interrupts Software modifications (implicit or explicit) of the PSW are done in the EXECUTE phase of the respective instructions.
Page 45 ST10R272L - CENTRAL PROCESSING UNIT direction should be followed by an instruction that does not access the same port, for example: WRONG: BSET DP3.13 ;change direction of P3.13 to output BSET P3.5 ;P3.13 is still input, the rd-mod-wr reads pin P3.13...
Page 46: Bit-Handling And Bit-Protection
The following section gives some hints on optimizing time-critical programs, with regard to the pipeline. Bit-handling and bit-protection The ST10R272L provides several bit manipulation mechanisms which manipulate software flags within the internal RAM, control on-chip peripherals via control bits in their respective SFRs, or control IO functions via port pins.
Page 47: Instruction Execution Time
The table below shows the minimum execution times required to process an instruction fetched from the internal RAM or from external memory. These execution times apply to most of the ST10R272L instructions - except for some branches, the multiplication and the division instructions and a special move instruction.
Page 48: Cpu Special Function Registers
ST10R272L - CENTRAL PROCESSING UNIT • External operand writes. • Testing Branch Conditions immediately after PSW writes. CPU special function registers Special Function Registers (SFRs) maintain the system state information, supply the ALU with register-addressable constants, control the system and bus configuration, multiply and divide ALU operations, code memory segmentation, data memory paging, and access the general purpose registers and the system stack.
Page 49 ST10R272L - CENTRAL PROCESSING UNIT Function Visible Mode Control VISIBLE ‘0’: Accesses to XBUS peripherals are done internally ‘1’: XBUS peripheral accesses are made visible on the external pins. Xperipheral SSP Enable Control SSPEN ‘0’: SSP is disabled. Pins P4.[7..4] are gen. purpose I/Os or segment address lines ‘1’: SSP is enabled.
Page 50 ST10R272L - CENTRAL PROCESSING UNIT Function Internal ROM Enable (Set according to pin EA during reset) ‘0’: Internal ROM disabled: accesses to the ROM area use the external bus ROMEN ‘1’: Internal ROM enabled This bit is not relevant on the ST10R262 since it does not include internal ROM. It...
Page 51 ST10R272L - CENTRAL PROCESSING UNIT available for instructions. For implicit stack operations (CALL or RET) the CSP register and the IP are saved to and restored from the stack. After reset, the segmented memory mode is selected. Note Bit SGTDIS controls whether the CSP register is pushed onto the system stack (in addition to the IP and PSW registers) before an interrupt service routine is entered, and whether it is re-popped when the interrupt service routine is left again.
Page 52 ST10R272L - CENTRAL PROCESSING UNIT Function End of Table Flag Set, when the source operand of an instruction is 8000h or 80h. Multiplication/Division In Progress MULIP ‘0’: There is no multiplication/division in progress. ‘1’: A multiplication/division has been interrupted. User General Purpose Flag USR0 May be used by the application software.
Page 53 ST10R272L - CENTRAL PROCESSING UNIT carry. The C-flag is always cleared for logical, multiply and divide ALU operations because these operations cannot cause a carry. For shift and rotate operations, the C-flag represents the value of the bit shifted out last. If a shift count of zero is specified, the C-flag will be cleared.
Page 54 ST10R272L - CENTRAL PROCESSING UNIT For the addition and subtraction with carry, the Z-flag is only set to ’1’ if the Z-flag already contains a ’1’ and the result of the current ALU operation additionally equals zero. This mechanism is provided for the support of multiple precision calculations.
Page 55 This register determines the 16-bit intra-segment address of the instruction in the code segment selected by the CSP register. The IP register is not mapped into the ST10R272L’s address space, and cannot be directly accessed by the programmer. The IP can, however, be modified indirectly via the stack, with a return instruction.
Page 56 ST10R272L - CENTRAL PROCESSING UNIT the RETS and RETI instructions. On the acceptance of an interrupt, or the execution of a software TRAP instruction, the CSP register is automatically set to zero CSP (FE08h / 04h) Reset Value: 0000h SEGNR...
Page 57 ST10R272L - CENTRAL PROCESSING UNIT The DPP registers are implicitly used whenever data accesses to any memory location are made via indirect or direct long 16-bit addressing modes (except for override accesses via EXTended instructions and PEC data transfers). After reset, the data page pointers are initialized in a way that all indirect or direct long 16-bit addresses result in identical 18-bit addresses.
Page 58 ST10R272L - CENTRAL PROCESSING UNIT page base-address, together with the 14-bit page-offset, forms the physical 24/20/18-bit address. For Non-segmented Memory Mode, only the two least significant bits of the implicitly selected DPP register are used to generate the physical address. Extreme care should be taken when changing the content of a DPP register if a non-segmented memory model is selected, otherwise unexpected results can occur.
Page 59 ST10R272L - CENTRAL PROCESSING UNIT Note Ensure that the physical GPR address specified by the CP register and short GPR address is always at an internal RAM location. Otherwise, unexpected results may occur. • Do not set CP below 00’F600h or above 00’FDFEh.
Page 60 ST10R272L - CENTRAL PROCESSING UNIT Figure 14 Register bank selection via the CP register Several addressing modes use the CP register for address calculations. Short 4-Bit GPR addresses (mnemonic: Rw or Rb) specify an address relative to the memory location specified by the contents of the CP register, i.e. the base of the current register bank.
Page 61 SP register can only contain values from F000h to FFFEh. This makes it possible to access a physical stack within the internal RAM of the ST10R272L. A virtual stack (usually bigger) can be realized via software. This mechanism is supported by registers STKOV and STKUN (see STKOV and STKUN descriptions below).
Page 62 ST10R272L - CENTRAL PROCESSING UNIT The SP register can be updated by any instruction which is capable of modifying an SFR. Due to the internal instruction pipeline, a POP or RETURN instruction must NOT immediately follow an instruction that updates the SP register.
Page 63 ST10R272L - CENTRAL PROCESSING UNIT six additional stack word locations are required to push IP, PSW, and CSP for both the interrupt-service routine and the hardware-trap service routine. STKOV (FE14h / 0Ah) Reset Value: FA00h stkov Function Modifiable portion of register STKOV stkov Specifies the lower limit of the internal system stack.
Page 64 ST10R272L - CENTRAL PROCESSING UNIT • the limits of the stack area (STKOV, STKUN) are changed, so that SP is outside of the new limits. STKUN (FE16h / 0Bh) Reset Value: FC00h stkun Function Modifiable portion of register STKUN stkun Specifies the upper limit of the internal system stack.
Page 65 ST10R272L - CENTRAL PROCESSING UNIT When a multiplication or division is interrupted before its completion, and when a new multiply or divide operation is to be performed within the interrupt service routine, registers MDL, MDH and MDC must be saved, to avoid erroneous results.
Page 66 ST10R272L - CENTRAL PROCESSING UNIT and should never be user modified. Otherwise, a correct continuation of an interrupted multiply or divide operation cannot be guaranteed. MDC (FF0Eh / 87h) Reset Value: 0000h Function MDRIU Multiply/Divide Register In Use ‘0’: Cleared, when register MDL is read via software.
Page 67 ST10R272L - CENTRAL PROCESSING UNIT manipulation or mask generation. It can be accessed via any instruction capable of addressing an SFR. ZEROS (FF1Ch / 8Eh) Reset Value: 0000h ONES (FF1Eh / 8Fh) Reset Value: FFFFh 66/320...
Page 68: Multiply-Accumulate Unit (Mac)
ST10R272L - MULTIPLY-ACCUMULATE UNIT (MAC) MULTIPLY-ACCUMULATE UNIT (MAC) The MAC is a specialized co-processor added to the ST10R272L CPU core to improve the performance of signal processing algorithms. It includes: • a multiply-accumulate unit • an address generation unit, able to feed the MAC unit with 2 operands per cycle •...
Page 69: Mac Features
ST10R272L - MULTIPLY-ACCUMULATE UNIT (MAC) MAC features Enhanced addressing capabilities • Double indirect addressing mode with pointer post-modification. • Parallel Data Move allows one operand move during Multiply-Accumulate instructions without penalty. • CoSTORE instruction (for fast access to the MAC SFRs) and CoMOV (for fast memory to memory table transfer).
Page 70: Mac Operation
ST10R272L - MULTIPLY-ACCUMULATE UNIT (MAC) MAC operation Operand1 Operand2 Interrupt Controller 16 x 16 signed/unsigned Multiplier Concatenation ST10 Core Sign Extend Scaler 08000h Repeat Unit 40-bit Signed Arithmetic Unit Flags MAE Control Unit Data 8-bit Left/Right Limiter Shifter Figure 17 MAC architecture 5.2.1...
Page 71: Address Generation
ST10R272L - MULTIPLY-ACCUMULATE UNIT (MAC) • EXECUTE: Performs the MAC operation. At the end of the cycle, the Accumulator and the MAC condition flags are updated if required. Modified GPR pointers are written-back during this stage, if required. • WRITEBACK: Operand write-back in the case of parallel data move.
Page 72 ST10R272L - MULTIPLY-ACCUMULATE UNIT (MAC) Symbol Mnemonic Address Pointer Operation ⊗]” stands for (Rwn) ← (Rwn) (no-op) “[Rw [Rwn] (Rwn) ← (Rwn) +2 (n=0-15) [Rwn+] (Rwn) ← (Rwn) -2 (k=0-15) [Rwn-] (Rwn) ← (Rwn) + (QR j ) (n=0-15;j =0,1) [Rwn+QR j ] (Rwn) ←...
Page 73: 16 X 16 Signed/Unsigned Parallel Multiplier
ST10R272L - MULTIPLY-ACCUMULATE UNIT (MAC) The Parallel Data Move shifts a table of operands in parallel with a computation on those operands. Its specific use is for signal processing algorithms like filter computation. The following figure gives an example of Parallel Data Move with CoMACM instruction.
Page 74: 40-Bit Accumulator Register
ST10R272L - MULTIPLY-ACCUMULATE UNIT (MAC) is fed either by the 40-bit shifted/not shifted and inverted/not inverted accumulator or by 00,0000,0000h. A-input and B-input ports can receive 00,0000,0000h to allow direct transfers from the B-source and A-source, respectively, to the Accumulator (case of Multiplication, Shift.).
Page 75: Accumulator Shifter
ST10R272L - MULTIPLY-ACCUMULATE UNIT (MAC) 5.2.7 Accumulator shifter The Accumulator shifter is a parallel shifter with a 40-bit input and a 40-bit output. The source operand of the shifter is the Accumulator and the possible shifting operations are: • No shift (Unmodified) •...
Page 76: Mac Interrupt
ST10R272L - MULTIPLY-ACCUMULATE UNIT (MAC) (minus 1) of repetition that remains to complete the sequence. If the Repeat Unit is used in the interrupt routine, MRW must be saved by the user and restored before the end of the interrupt routine.
Page 77: 10Number Representation & Rounding
ST10R272L - MULTIPLY-ACCUMULATE UNIT (MAC) 5.2.10 Number representation & rounding The MAC supports the two’s-complement representation of binary numbers. In this format, the sign bit is the MSB of the binary word. This is set to zero for positive numbers and set to one for negative numbers.
Page 78: Mac Register Set
ST10R272L - MULTIPLY-ACCUMULATE UNIT (MAC) MAC register set 5.3.1 Address registers The new addressing modes require new (E)SFRs: 2 address pointers IDX0 / IDX1 and 4 offset registers QX0 / QX1 and QR0 / QR1. IDX0 (FF08h / 84h) Reset Value: 0000h...
Page 79 ST10R272L - MULTIPLY-ACCUMULATE UNIT (MAC) MAH and MAL are located in the non bit-addressable SFR space. MAH (FE5Eh / 2Fh) Reset Value: 0000h Function MAC Unit Accumulator High (bits [31..16]) MAL (FE5Ch / 2Eh) Reset Value: 0000h Function MAC Unit Accumulator Low (bits [15..0])
Page 80 ST10R272L - MULTIPLY-ACCUMULATE UNIT (MAC) Function Sticky Overflow Flag Set when a MAC operation produces a 40-bit arithmetic overflow. It remains set until it is explicitly reset by software. Carry Flag Set when a MAC operation produces a carry or a borrow bit.
Page 81 ST10R272L - MULTIPLY-ACCUMULATE UNIT (MAC) MCW (FFDCH / EEh Reset Value: 0000h Function MAC Interrupt Enable ‘0’: MAC interrupt globally disabled, ‘1’: MAC interrupt globally enabled. SL Mask When set, the SL Flag can generate a MAC interrupt request. E Mask When set, the E Flag can generate a MAC interrupt request.
Page 82: Mac Instruction Set Summary
ST10R272L - MULTIPLY-ACCUMULATE UNIT (MAC) Function 13-bit unsigned integer value Repeat Count Indicates the number of time minus one a repeated instruction must be executed. Note As for the CPU Core SFRs, any write operation with the regular instruction set to a single byte of a MAC SFR clears the non-addressed complementary byte within the specified SFR.
Page 83 ST10R272L - MULTIPLY-ACCUMULATE UNIT (MAC) Mnemonic Addressing Modes Mnemonic Addressing Modes ⊗], [Rw ⊗] CoMUL , Rw CoMACM [IDX ⊗], [Rw ⊗] CoMULu [IDX CoMACMu ⊗] CoMULus , [Rw CoMACMus CoMULsu CoMACMsu CoMUL- CoMACM- CoMULu- CoMACMu- CoMULus- CoMACMus- CoMULsu- CoMACMsu-...
Page 84: Interrupt And Trap Functions
(rising edge, falling edge or both edges). Interrupt system structure The ST10R272L provides 20 separate interrupt nodes that may be assigned to 16 priority levels. In order to support modular and consistent software design techniques, each source of an interrupt or PEC request is supplied with a separate interrupt control register and interrupt vector.
Page 85: Interrupt Sources
The reserved vector locations build a Jump Table in the low end of the ST10R272L’s address space (segment 0). The Jump Table is made up of jump instructions that transfer control to the interrupt or trap service routines which may be located anywhere in the address space.
Page 86: Normal Interrupt Processing And Pec Service
ST10R272L - INTERRUPT AND TRAP FUNCTIONS Source of Interrupt or PEC Request Enable Interrupt Vector Trap Service Request Flag Flag Vector Location Number External Interrupt 3 CC11IR CC11IE CC11INT GPT1 Timer 2 T2IR T2IE T2INT GPT1 Timer 3 T3IR T3IE...
Page 87: Interrupt System Registers
ST10R272L - INTERRUPT AND TRAP FUNCTIONS 6.1.3 Interrupt system registers Interrupt processing is controlled globally by the PSW register through the general interrupt enable bit (IEN) and the CPU priority field (ILVL). Additionally, the different interrupt sources are controlled individually by their specific interrupt control registers (...IC). Therefore, the CPU accepts requests based on the individual interrupt control registers and the PSW.
Page 88 ST10R272L - INTERRUPT AND TRAP FUNCTIONS xxIC (yyyyh / zzh) Reset Value: - - 00h xxIR xxIE ILVL GLVL Function Group Level Defines the internal order for simultaneous requests of the same priority. GLVL 3: Highest group priority 0: Lowest group priority Interrupt Priority Level Defines the priority level for the arbitration of requests.
Page 89 ST10R272L - INTERRUPT AND TRAP FUNCTIONS Note Modifying the interrupt request flag by software causes the same effects as if it had been set or cleared by hardware. All interrupt request sources that are enabled and programmed to the same priority level must always be programmed to different group priorities.
Page 90: Interrupt Control Functions In The Psw
ST10R272L - INTERRUPT AND TRAP FUNCTIONS GLVL ILVL interrupt control register PEC Control PEC channel Figure 20 Priority levels and PEC channels The following table shows - in a few examples - where an action is triggered by the programming of an interrupt control register.
Page 91 ST10R272L - INTERRUPT AND TRAP FUNCTIONS interrupt system of the ST10R272L and the arbitration mechanism for the external bus interface. Note Pipeline effects must be considered when enabling/disabling interrupt requests by modifying the PSW register (ref to “Processor status word PSW” on page 50).
Page 92: Operation Of The Pec Channels
ST10R272L - INTERRUPT AND TRAP FUNCTIONS Note The TRAP instruction does not change the CPU level, therefore, software invoked trap service routines may be interrupted by higher requests. Interrupt Enable bit IEN globally enables or disables PEC operation and the acceptance of interrupts by the CPU.
Page 93 ST10R272L - INTERRUPT AND TRAP FUNCTIONS Register Address Reg. Space Register Address Reg. Space PECC0 FEC0h / 60h PECC4 FEC8h / 64h PECC1 FEC2h / 61h PECC5 FECAh / 65h PECC2 FEC4h / 62h PECC6 FECCh / 66h PECC3 FEC6h / 63h...
Page 94 These pointers do not reside in specific SFRs, but are mapped into the internal RAM of the ST10R272L just below the bit-addressable area (see figure below). PEC data transfers do not use the data page pointers DPP3...DPP0. The PEC source and destination pointers are used as 16-bit intra-segment addresses within segment 0, so that data can be transferred between any two locations in the first four data pages 3...0.
Page 95: Prioritizing Interrupt And Pec Service Requests
ST10R272L - INTERRUPT AND TRAP FUNCTIONS Address Address DSTP7 DSTP3 00’FCFEh 00’FCEEh SRCP7 SRCP3 00’FCFCh 00’FCECh DSTP6 DSTP2 00’FCFAh 00’FCEAh SRCP6 SRCP2 00’FCF8h 00’FCE8h DSTP5 DSTP1 00’FCF6h 00’FCE6h SRCP5 SRCP1 00’FCF4h 00’FCE4h DSTP4 DSTP0 00’FCF2h 00’FCE2h SRCP4 SRCP0 00’FCF0h 00’FCE0h...
Page 96: Interrupt Class Management
ST10R272L - INTERRUPT AND TRAP FUNCTIONS does not require to re-enable the interrupt system after the inseparable instruction sequence. Interrupt class management An interrupt class covers a set of interrupt sources with the same priority. Interrupts of the same class must not interrupt each other. This is supported with two features: •...
Page 97: Saving The Status During Interrupt Service
ST10R272L - INTERRUPT AND TRAP FUNCTIONS GLVL ILVL Interpretation (Priority) Interrupt class-2: 10 sources on 3 levels Interrupt class-3: 6 sources on 2 levels No service! Table 17 Software controlled interrupt classes (example) Saving the status during interrupt service Before an arbitrated interrupt request is serviced, the status of the current task is automatically saved on the system stack.
Page 98: Context Switching
The more registers a routine uses, the more time is taken by saving and restoring. The ST10R272L is able to switch the complete bank of CPU registers (GPRs) with a single instruction, so the service routine executes within its own, separate context.
Page 99: Interrupt Response Times
ST10R272L - INTERRUPT AND TRAP FUNCTIONS Interrupt response times The interrupt response time defines the time between the setting of an interrupt request flag to the first instruction fetch from the interrupt vector location (I1). The basic interrupt response time is 3 instruction cycles.
Page 100 ST10R272L - INTERRUPT AND TRAP FUNCTIONS Pipeline Stage Cycle 1 Cycle 2 Cycle 3 Cycle 4 N + 1 N + 2 FETCH N - 1 TRAP (1) TRAP (2) DECODE N - 2 N - 1 TRAP EXECUTE N - 3...
Page 101: Pec Response Times
ST10R272L - INTERRUPT AND TRAP FUNCTIONS • When instructions N, N+1 and N+2 are executed out of external memory and the interrupt vector also points to an external location, but all operands for instructions N-3 through N are in internal memory, then the interrupt response time is the time to perform 3 word bus-accesses.
Page 102 ST10R272L - INTERRUPT AND TRAP FUNCTIONS When the interrupt request flag is set during the first CPU clock cycle of an instruction, the minimum PEC response time is 4 CPU clock cycles. Pipeline Stage Cycle 1 Cycle 2 Cycle 3...
Page 103: External Interrupts
(HOLD mode). External interrupts Although the ST10R272L has no dedicated INTR input pins, it can react to external asynchronous events by using the IO lines for interrupt input. The interrupt function can be combined with the pin’s main function or can be used instead of it, i.e. if the main pin function is not required.
Page 104: Fast External Interrupts
The input pins that may be used for external interrupts are sampled every 8 CPU clock cycles, i.e. external events are scanned and detected in time-frames of 8 CPU clock cycles. The ST10R272L provides 4 interrupt inputs that are sampled every CPU clock cycle, so external events are captured faster than with standard interrupt inputs.
Page 105 ST10R272L - INTERRUPT AND TRAP FUNCTIONS EXICON (F1C0h / E0h) ESFR Reset Value: 0000h EXI3ES EXI2ES EXI1ES EXI0ES CCxIC (seeTable 19) Reset Value: --00h GLVL ILVL Function External Interrupt x Edge Selection Field (x=3...0) 0 0: Fast external interrupts disabled: standard mode...
Page 106: Traps
ST10R272L - INTERRUPT AND TRAP FUNCTIONS Note Refer to “Interrupt control registers” on page 86 for an explanation of the control fields. Traps 6.9.1 Software traps Software Traps can be performed from any vector location between 00’0000h and 00’01FCh. A service routine entered via a software TRAP instruction, is always executed on the current CPU priority level (indicated in bit field ILVL in register PSW).
Page 107: Trap Flag Register
ST10R272L - INTERRUPT AND TRAP FUNCTIONS Vector Trap Trap Exception Condition Trap Flag Trap Vector Location Number Priority Hardware Reset RESET 00’0000 Software Reset RESET 00’0000 Watchdog Timer Overflow RESET 00’0000 class-A Hardware Traps: Non-Maskable Interrupt NMITRAP 00’0008 Stack Overflow...
Page 108 PRTFLT A protected instruction with an illegal format has been detected. Undefined Opcode Flag UNDOPC The currently decoded instruction has no valid ST10R272L opcode. Stack Underflow Flag STKUF The current stack pointer value exceeds the content of register STKUN. Stack Overflow Flag STKOF The current stack pointer value falls below the content of register STKOV.
Page 109: External Nmi Trap
ST10R272L - INTERRUPT AND TRAP FUNCTIONS All class-B traps have the same trap priority (trap priority I). When several class-B traps get active at a time, the corresponding flags in the TFR register are set and the trap service routine is entered. Since all class-B traps have the same vector, the priority of service of simultaneously occurring class-B traps is determined by software in the trap service routine.
Page 110: Undefined Opcode Trap
6.9.7 Undefined opcode trap When the instruction currently decoded by the CPU does not contain a valid ST10R272L opcode, the UNDOPC flag is set in register TFR and the CPU enters the undefined opcode trap routine. The IP value pushed onto the system stack is the address of the instruction that caused the trap.
Page 111: 12Mac Interrupt On Condition
ST10R272L - INTERRUPT AND TRAP FUNCTIONS 6.9.12 MAC interrupt on condition User defined in the MCW register. 110/320...
Page 112: Parallel Ports
ST10R272L - PARALLEL PORTS PARALLEL PORTS The ST10R272L provides up to 77 parallel I/O lines organized into six 8-bit I/O ports (POH, POL, P1H, P1L, P4, P6), two 4-bit I/O ports (P2, P7), one 15 bit I/O port (P3) and one 6-bit input port (P5).
Page 113 Note E denotes an ESFR located in the ESFR space In the ST10R272L certain ports provide Open Drain Control, which allows to switch the output driver of a port pin from a push/pull configuration to an open drain configuration. In push/pull mode a port output driver has an upper and a lower transistor, thus it can actively drive the line either to a high or a low level.
Page 114 ST10R272L - PARALLEL PORTS • Each port line has one programmable alternate input or output function associated with it. PORT0 and PORT1 may be used as the address and data lines when accessing external memory. • Port 2 is used for fast external interrupt inputs.
Page 115 ST10R272L - PARALLEL PORTS purposes to allow a software trigger of an alternate input function by writing to the port output latch. On most of the port lines, the user software is responsible for setting the proper direction when using an alternate input or output function of a pin. This is done by setting or clearing the direction control bit DPx.y of the pin before enabling the alternate function.
Page 116: Port 0
ST10R272L - PARALLEL PORTS Port 0 The two 8-bit ports P0H and P0L represent the higher and lower part of PORT0, respectively. Both halves of PORT0 can be written (e.g. via a PEC transfer) without affecting the other half. If this port is used for general purpose I/O, the direction of each line can be configured via the corresponding direction registers DP0H and DP0L.
Page 117: Alternate Functions Of Port0
ST10R272L - PARALLEL PORTS 7.1.1 Alternate functions of PORT0 When an external bus is enabled, PORT0 is used as data bus or address/data bus. Note that an external 8-bit demultiplexed bus only uses P0L, while P0H is free for I/O (provided that no other bus mode is enabled).
Page 118 ST10R272L - PARALLEL PORTS outputting the address. During external accesses in demultiplexed bus modes PORT0 reads the incoming instruction or data word or outputs the data byte or word. Alternate Function AD15 AD15 P0H.7 AD14 AD14 P0H.6 AD13 AD13 P0H.5...
Page 119: Port 1
ST10R272L - PARALLEL PORTS The figure below shows the structure of a PORT0 pin. Figure 28 Block diagram of a PORT0 pin Port 1 The two 8-bit ports P1H and P1L represent the higher and lower part of PORT1, respectively. Both halves of PORT1 can be written (e.g. via a PEC transfer) without affecting...
Page 120: Alternate Functions Of Port1
ST10R272L - PARALLEL PORTS the other half. If this port is used for general purpose I/O, the direction of each line can be configured via the corresponding direction registers DP1H and DP1L. P1L (FF04h / 82h) Reset Value: - - 00h P1L.7...
Page 121 ST10R272L - PARALLEL PORTS During external accesses in demultiplexed bus modes PORT1 outputs the 16-bit intra-segment address as an alternate output function. During external accesses in multiplexed bus modes, when no BUSCON register selects a demultiplexed bus mode, PORT1 is not used and is available for general purpose I/O.
Page 122: Port 2
ST10R272L - PARALLEL PORTS The figure below shows the structure of a PORT1 pin. Figure 30 Block diagram of a PORT1 pin Port 2 Port 2 is a 4-bit port. If Port 2 is used for general purpose I/O, the direction of each line can be configured via the corresponding direction register DP2.
Page 123 ST10R272L - PARALLEL PORTS DP2 (FFC2h/ E1h) Reset Value: 00 - -h Function Port direction register DP2 bit y DP2.y DP2.y = 0: Port line P2.y is an input (high-impedance) DP2.y = 1: Port line P2.y is an output ODP2 (F1C2h / E1h)
Page 124: Port 3
ST10R272L - PARALLEL PORTS Alternate Function EX3IN P2.11 EX2IN P2.10 EX1IN P2.9 EX0IN P2.8 Port 2 General Fast External Purpose Interrupt Input Figure 31 Port 2 I/O and alternate functions 123/320...
Page 125 ST10R272L - PARALLEL PORTS The pins of Port 2 combine internal bus data and alternate data output before the port latch input. y = 11...8 Figure 32 Block diagram of a port 2 pin Port 3 If this 15-bit port is used for general purpose I/O, the direction of each line can be configured via the corresponding direction register DP3.
Page 126: Alternate Functions Of Port 3
ST10R272L - PARALLEL PORTS Due to pin limitations register bit P3.14 is not connected to an output pin. P3 (FFC4h / E2h) Reset Value: 0000h P3.15 P3.13 P3.12 P3.11 P3.10 P3.9 P3.8 P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 Function P3.y...
Page 127 ST10R272L - PARALLEL PORTS The table below summarizes the alternate functions of Port 3. . Port 3 Pin Alternate Function P3.0 P3.1 T6OUT Timer 6 Toggle Output P3.2 CAPIN GPT2 Capture Input P3.3 T3OUT Timer 3 Toggle Output P3.4 T3EUD...
Page 128 ST10R272L - PARALLEL PORTS When the on-chip peripheral associated with a Port 3 pin is configured to use the alternate input function, it reads the input latch, which represents the state of the pin, via the line labeled “Alternate Data Input”. Port 3 pins with alternate input functions are: T2IN, T3IN, T4IN, T3EUD and CAPIN.
Page 129 ST10R272L - PARALLEL PORTS Enabling the CLKOUT function automatically enables the P3.15 output driver. Setting bit DP3.15=’1’ is not required. y = 13, 11...0 Figure 35 Block diagram of port 3 pin with alternate input or alternate output function Pin P3.12 (BHE/WRH) is one more pin with an alternate output function. However, its structure is slightly different (see figure below), because after reset the BHE or WRH function must be used depending on the system start-up configuration.
Page 130: Port 4
Figure 36 Block diagram of pins P3.15 (CLKOUT) and P3.12 (BHE/WRH) Port 4 In the ST10R272L, the Port 4 is an 8-bit port. If the SSP is disabled (bit SSPEN cleared in SYSCON register), Port 4 is used for general purpose I/O (the direction of each line can be configured via the corresponding direction register DP4).
Page 131: Alternate Functions Of Port 4
ST10R272L - PARALLEL PORTS Control Register (DP4) that correspond to the pins SSPCLK, SSPDATA, SSPDEN0 and SSPDEN1 are no influence on these pins. P4 (FFC8h / E4h) Reset Value: - - 00h P4.7 P4.6 P4.5 P4.4 P4.3 P4.2 P4.1 P4.0 Function P4.y...
Page 132 ST10R272L - PARALLEL PORTS The table below summarizes the alternate functions of Port 4 depending on the number of selected segment address lines (coded via bitfield SALSEL) and on the state of SSPEN control bit..Std. Function Altern. Function Altern. Function Altern.
Page 133 ST10R272L - PARALLEL PORTS Write DP4.y Direction Latch Read DP4.y Alternate Function Enable Alternate Write P4.y Data Output P4.y Port Output Output Latch Buffer Read P4.y Clock Input Latch VR02075B y = 3...0 Figure 39 Block diagram of port 4 pin P4.0 to P4.3 Write DP4.y...
Page 134: Port 5
Port 5 pins are 5 V tolerant and fail-safe (voltage max. with respect to Vss is -0.5 to 5.5, even if the chip is non powered). For more information on this refer to the ST10R272L Data Sheet. This 6-bit input port can only read data. There is no output latch and no direction register.
Page 135: Alternate Functions Of Port 5
ST10R272L - PARALLEL PORTS 7.6.1 Alternate functions of port 5 Each line of Port 5 serves as external timer control line for GPT1 and GPT2. The table below summarizes the alternate functions of Port 5. . Port 5 Pin Alternate Function P5.10...
Page 136: Port 6
ST10R272L - PARALLEL PORTS y = 15...10 Figure 43 Block diagram of a port 5 pin Port 6 Port 6 is an 8-bit port that can be used for general purpose I/O. The direction of each line can be configured via the corresponding direction register DP6. Each port line can be switched into push/pull or open drain mode via the open drain control register ODP6.
Page 137: Alternate Functions Of Port 6
(BUSCON4...BUSCON0) can be output on 5 pins of Port 6. The other 3 pins may be used for bus arbitration to accommodate additional masters in a ST10R272L system. The number of chip select signals is selected via PORT0 during reset. The selected value can be read from bitfield CSSEL in register RP0H (read only) e.g.
Page 138 ST10R272L - PARALLEL PORTS The table below summarizes the alternate functions of Port 6, as a function of the number of selected chip select lines (coded via bitfield CSSEL). Altern. Function Altern. Function Altern. Function Altern. Function Port 6 CSSEL = 10...
Page 139 ST10R272L - PARALLEL PORTS • if the Port 6 line is used as a chip select output, and the ST10R272L is in Hold mode (invoked through HOLD), and the respective pin driver is in push/pull mode (ODP6.x = ‘0’). This feature is implemented to drive the chip select lines high during reset in order to avoid multiple chip selection, and to allow another master to access the external memory via the same chip select lines (Wired-AND), while the ST10R272L is in Hold mode.
Page 140 ST10R272L - PARALLEL PORTS The bus arbitration signals HOLD, HLDA and BREQ are selected with bit HLDEN in register PSW. When the bus arbitration signals are enabled via HLDEN, also these pins are switched automatically to the appropriate direction. Note that the pin drivers for HLDA and BREQ are automatically enabled, while the pin driver for HOLD is automatically disabled.
Page 141: Port 7
ST10R272L - PARALLEL PORTS Port 7 Port7 is a 4-bit port. If Port 7 is used for general purpose I/O, the direction of each line can be configured via the corresponding direction register DP7. Each port line can be switched into push/pull or open drain mode via the open drain control register ODP7.
Page 142: Alternate Functions Of Port 7
ST10R272L - PARALLEL PORTS 7.8.1 Alternate functions of Port 7 The table below summarizes the alternate functions of Port 7. Port 7Pin Alternate Function P7.3 POUT3 PWM (Channel 3) Output Table 23 Port 7 alternate functions Alternate Function Port 7 P7.3...
Page 143 ST10R272L - PARALLEL PORTS y= 3...0 Figure 49 Block diagram of a port 7 pin (P7.3..P7.0) The port structure of pins p7.0 through P7.3 is similar to the structure of Port3 pins with an alternate output function (e.g. T3OUT, T6OUT, etc.), as it is described in “Alternate functions of Port 3”...
Page 144: Dedicated Pins
ST10R272L - DEDICATED PINS DEDICATED PINS Most of the input/output or control signals of the functional the ST10R272L are realized as alternate functions of pins of the parallel ports. There is, however, a number of signals that use separate pins, including the oscillator, special control signals and the power supply.
Page 145 An external clock signal may be fed to the input XTAL1, leaving XTAL2 open. Digital Power Supply and Ground (6 pins each): provides the power supply for the digital logic of the ST10R272L. All V pins and all V pins must be con- nected to the power supply and ground, respectively.
Page 146: External Bus Interface
ST10R272L - EXTERNAL BUS INTERFACE EXTERNAL BUS INTERFACE Although the ST10R272L provides a powerful set of on-chip peripherals and on-chip RAM areas, these internal units only cover a small fraction of its address space of up to 16 MByte. The external bus interface is used to access external peripherals and additional volatile and non-volatile memory.
Page 147: Single Chip Mode
PORT0 for input/output. When the external bus interface is enabled and configured (bit BUSACTx=’1’ and bitfield BTYP), the ST10R272L uses a subset of its port lines together with some control lines to build the external bus. The bus configuration (BTYP) for the address windows (BUSCON4...BUSCON1) is selected via software typically during the initialization of the system.
Page 148: Multiplexed Bus Modes
ST10R272L - EXTERNAL BUS INTERFACE In this case Port 4 outputs four, two or no address lines at all. It outputs all 8 address lines, if an address space of 16 MBytes is used. Note When the on-chip SSP Module is to be used the segment address output on Port 4 must be limited to 4 bits (i.e.
Page 149: Demultiplexed Bus Modes
ST10R272L - EXTERNAL BUS INTERFACE Write cycles: The command signal is now deactivated. The data remain valid on the bus until the next external bus cycle is started. Figure 52 Multiplexed bus cycle 9.2.2 Demultiplexed bus modes In the demultiplexed bus modes the 16-bit intra-segment address is permanently output on PORT1, while the data uses PORT0 (16-bit data) or P0L (8-bit data).
Page 150: Switching Between Bus Modes
ST10R272L - EXTERNAL BUS INTERFACE Write cycles: The command signal is now deactivated. If a subsequent external bus cycle is required, the EBC places the respective address on the address bus. The data remain valid on the bus until the next external bus cycle is started.
Page 151 ST10R272L - EXTERNAL BUS INTERFACE PORT1 will output the intra-segment address, when any of the BUSCON registers selects a demultiplexed bus mode, even if the current bus cycle uses a multiplexed bus mode. This allows to have an external address decoder connected to PORT1 only, while using it for all kinds of bus cycles.
Page 152: External Data Bus Width
ST10R272L - EXTERNAL BUS INTERFACE This extra time is required to allow the previously selected device (via demultiplexed bus) to release the data bus, which would be available in a demultiplexed bus cycle. Figure 54 Switching from demultiplexed to multiplexed bus mode 9.2.4...
Page 153: Disable/Enable Control For Pin Bhe (Bytdis)
When reading bytes from an external 16-bit device, whole words may be read and the ST10R272L automatically selects the byte to be input and discards the other. However, care must be taken when reading devices that change state when being read, like FIFOs, interrupt status registers, etc.
Page 154: Cs Signal Generation
ST10R272L - EXTERNAL BUS INTERFACE Note The total accessible address space may be increased by accessing several banks which are distinguished by individual chip select signals. Segment Address SALSEL Directly accessible Address Space Lines Two: A17...A16 KByte (default without pulldowns) Eight: A23...A16...
Page 155: Segment Address Versus Chip Select
The external bus interface of the ST10R272L supports many configurations for the external memory. By increasing the number of segment address lines the ST10R272L can address a linear address space of 256 KByte, 1 MByte or 16 MByte. This allows to implement a large sequential memory area, and also allows to access a great number of external devices, using an external decoder.
Page 156: Programmable Bus Characteristics
ST10R272L - EXTERNAL BUS INTERFACE access memory banks or peripherals without external glue logic. These two features may be combined to optimize the overall system performance. Enabling 4 segment address lines and 5 chip select lines e.g. allows to access five memory banks of 1 MByte each. So the available address space is 5 MByte (without glue logic).
Page 157: Ale Length Control
ST10R272L - EXTERNAL BUS INTERFACE Internal accesses are executed with maximum speed and therefore are not programmable. External accesses use the slowest possible bus cycle after reset. The bus cycle timing may then be optimized by the initialization software. Figure 55 Programmable external bus cycle 9.3.1...
Page 158: Programmable Memory Cycle Time
9.3.2 Programmable memory cycle time The ST10R272L allows the user to adjust the controller’s external bus cycles to the access time of the respective memory or peripheral. This access time is the total time required to move the data to the destination. It represents the period of time during which the controller’s signals do not change.
Page 159: Programmable Memory Tri-State Time
ST10R272L - EXTERNAL BUS INTERFACE The memory cycle time wait states can be programmed in increments of one CPU clock within a range from 0 to 15 (default after reset) via the MCTC fields of the BUSCON registers. 15-<MCTC> waitstates will be inserted.
Page 160: Read/Write Delay Time
The read/write delay does not extend the memory cycle time, and does not slow down the controller in general. In multiplexed bus modes, however, the data drivers of an external device may conflict with the ST10R272L’s address, when the early RD signal is used. Therefore multiplexed bus cycles should always be programmed with read/write delay.
Page 161: Ready/Ready Controlled Bus Cycles
Where the programmable waitstates are not enough, or where the response (access) time of a peripheral is not constant, the ST10R272L provides external bus cycles that are terminated by a READY or READY input signal (synchronous or asynchronous). In this case the ST10R272L first inserts a programmable number of waitstates (0...7) and then monitors...
Page 162 ST10R272L - EXTERNAL BUS INTERFACE When the READY or READY function is enabled for a specific address window, each bus cycle in this window must be terminated with the active level defined by the RDYPOL bit 13 in the associated BUSCON register.
Page 163: Programmable Chip Select Timing Control
READY/READY output. After the predefined number of waitstates the ST10R272L will check its READY/READY line to determine the end of the bus cycle. For a memory access it will be low already (see example a in the figure above), for a peripheral access it may be delayed (see example b in the figure above).
Page 164: Controlling The External Bus Controller
ST10R272L - EXTERNAL BUS INTERFACE Normal Demultiplexed ALE Lengthen Demultiplexed Bus Cycle Bus Cycle Address (P1) Segment (P4) Normal CSx Unlatched CSx Data Data BUS (P0) BUS (P0) Data Data Read/Write Read/Write Delay Delay Figure 61 Chip select delay Controlling the external bus controller A set of registers controls the EBC.
Page 165: Registers
ST10R272L - EXTERNAL BUS INTERFACE 9.4.1 Registers SYSCON (FF12h / 89h) Reset Value: 0XX0h) VISI XPER- STKSZ SHARE Function XBUS Peripheral Share Mode Control XPER- ‘0’: External accesses to XBUS peripherals are disabled SHARE ‘1’: XBUS peripherals are accessible via the external bus during hold mode.
Page 166 ST10R272L - EXTERNAL BUS INTERFACE Function System Clock Output Enable (CLKOUT) CLKEN ‘0’: CLKOUT disabled: pin may be used for general purpose IO ‘1’: CLKOUT enabled: pin outputs the system clock signal Disable/Enable Control for Pin BHE (Set according to data bus width) BYTDIS ‘0’: Pin BHE enabled...
Page 167 ST10R272L - EXTERNAL BUS INTERFACE BUSCON0 (FF0Ch / 86h) Reset Value: 0XX0h BTYP MCTC ACT0 CTL0 POL0 BUSCON1 (FF14h / 8Ah) Reset Value: 0000h BTYP MCTC ACT1 CTL1 POL1 BUSCON2 (FF16h / 8Bh) Reset Value: 0000h BTYP MCTC ACT2 CTL2...
Page 168 ST10R272L - EXTERNAL BUS INTERFACE Function Memory Tristate Time Control MTTCx ‘0’: 1 waitstate ‘1’: No waitstate External Bus Configuration 0 0: 8-bit Demultiplexed Bus 0 1: 8-bit Multiplexed Bus BTYPx 1 0: 16-bit Demultiplexed Bus 1 1: 16-bit Multiplexed Bus Note: For BUSCON0 BTYP is defined via PORT0 during reset.
Page 169 ST10R272L - EXTERNAL BUS INTERFACE ADDRSEL1 (FE18h / 0Ch) Reset Value: 0000h RGSAD RGSZ ADDRSEL2 (FE1Ah / 0Dh) Reset Value: 0000h RGSAD RGSZ ADDRSEL3(FE1Ch / 0Eh) Reset Value: 0000h RGSAD RGSZ ADDRSEL4 (FE1Eh / 0Fh) Reset Value: 0000h RGSAD RGSZ...
Page 170: Defining Address Areas
Defining address areas The four register pairs BUSCON4/AD-DRSEL4...BUSCON1/ADDRSEL1 are used to define 4 separate address areas within the address space of the ST10R272L. Within each of these address areas external accesses can be controlled by one of the four different bus modes, independent of each other and of the bus mode specified in register BUSCON0.
Page 171 ST10R272L - EXTERNAL BUS INTERFACE • The other group with ADDRSEL3 and ADDRSEL4, gives to ADDRSEL4 a higher priority than ADDRSEL3. Thus, an overlapping among address areas defined via registers ADDRSEL3 and 4 is allowed. The BUSCON0 register always has the lowest priority, and its address area can be overlapped by any of the other ADDRSELs.
Page 172 ST10R272L - EXTERNAL BUS INTERFACE RP0H (F108h / 84h) Reset Value: - - XXh CLKSEL SALSEL CSSEL Function Write Configuration Control WRCFG ‘0’: Pins WR and BHE retain their normal function ‘1’: Pins WR acts as WRL, pin BHE acts as WRH...
Page 173: Precautions And Hints
ST10R272L. During this time the ST10R272L can keep on executing, as long as it does not need access to the external bus. All actions that just require internal resources like instruction or data memory and on-chip peripherals, may be executed in parallel.
Page 174: Entering The Hold State
ST10R272L - EXTERNAL BUS INTERFACE When the ST10R272L needs access to its external bus while it is occupied by another bus master, it demands it via the BREQ output. The external bus arbitration is enabled by setting bit HLDEN in register PSW to ‘1’. This bit may be cleared during the execution of program sequences, where the external resources are required but cannot be shared with other bus masters.
Page 175: Exiting The Hold State
ST10R272L - EXTERNAL BUS INTERFACE Should the ST10R272L require access to its external bus during hold mode, it activates its bus request output BREQ to notify the arbitration circuitry. BREQ is activated only during hold mode. It will be inactive during normal operation.
Page 176: The Xbus Interface
ST10R272L - EXTERNAL BUS INTERFACE the ST10R272L needs access to the shared resources and demands this by activating its BREQ output. The arbitration logic may then deactivate the other master’s HLDA and so free the external bus for the ST10R272L, depending on the priority of the different masters.
Page 177 Interrupt nodes and configuration pins (on PORT0) are provided for X-Peripherals to be integrated. Note If you plan to develop your own peripheral for integration into a ST10R272L device, contact the Technical Support group for the further specification of the XBUS. 176/320...
Page 178: Pwm Module
ST10R272L - PWM MODULE PWM MODULE A 1-channel pulse width modulation (PWM) module is implemented in the ST10R272L. The minimum PWM signal frequency depends on the width (16 bits) and the resolution (CLK/1 or CLK/64) of the PWM timer. The maximum PWM signal frequency assumes that the PWM output signal changes with every cycle of the timer.
Page 179: Operating Modes
ST10R272L - PWM MODULE operation of channel 3 is controlled by the PWMCON0 and PWMCON1registers, and the interrupt control and status is handled by the PWMIC interrupt control register. PPx Period Register Comparator Up/Down 16-Bit Up/Down Clear : 64 Counter Control P7.x...
Page 180: 1Mode 0 - Standard Pwm Generation (Edge Aligned Pwm)
ST10R272L - PWM MODULE Note The output of the PWM module is EXORed with the output of the port output latch (P7.3). After reset, this latch is cleared, so the PWM signal is directly driven to the port pin. By setting the port output latch to ‘1’, the PWM signal is inverted (XORed with ‘1’) before being driven to the port pin.
Page 181 ST10R272L - PWM MODULE of the output signal. The negative edge is always fixed and related to the clearing of the timer. Period=7 PT3 Count Value Duty Cycle PW3=0 100% PW3=1 87.5% PW3=2 PW3=4 PW3=6 PW3=7 12.5% PW3=8 Latch Shadow Register...
Page 182: 2Mode 1 - Symmetrical Pwm Generation (Center Aligned)
ST10R272L - PWM MODULE 10.1.2 Mode 1 - symmetrical PWM generation (center aligned) Mode 1 is selected by setting bit PM3 in register PWMCON1 to ‘1’. In this mode, the PWM timer PT3 is counts up until it reaches the value in the period register PP3. On the next count pulse, the count direction is reversed and the timer starts counting down with subsequent count pulses until it reaches the value 0000h.
Page 183: 3Single Shot Mode
ST10R272L - PWM MODULE PWM, because the value in the pulse width (shadow) register affects both edges of the output signal symmetrically. Period=7 PT3 Count Value Duty Cycle PW3=0 100% PW3=1 87.5% PW3=2 PW3=4 PW3=6 PW3=7 12.5% PW3=8 Change Count...
Page 184 ST10R272L - PWM MODULE After starting the timer (i.e. PTR3 = ‘1’), the output pulse may be modified via software. Writing to timer PT3 changes the positive and/or negative edge of the output signal, depending on whether the pulse has already started (i.e. the output is high) or not (i.e. the output is still low).
Page 185 ST10R272L - PWM MODULE By setting the period (PP3), the timer start value (PT3) and the pulse width value (PW3) appropriately, the pulse width (tw) and the optional pulse delay (td) may varied in a wide range. Period=7 PT3 Count...
Page 186: Pwm Module Registers
ST10R272L - PWM MODULE 10.2 PWM module registers The PWM module is controlled by two sets of registers. The waveforms are selected by the timer register PT3, the period register PP3 and the pulse width register PW3. Three registers control the operating mode and the general functions (PWMCON0 and PWMCON1) of the PWM module and the interrupt behavior (PWMIC).
Page 187: 3Pulse Width Register Pw3
ST10R272L - PWM MODULE with the contents of the associated counter PT3. When a match is found between the counter and PP3 register, the counter is either reset to 0000h, or the count direction is switched from counting up to counting down, depending on the selected operating mode of that PWM channel.
Page 188: 5Pwm Control Register Pwmcon1
ST10R272L - PWM MODULE PWMCON0 (FF30h / 98h) Reset Value: 0000h PIR3 PIE3 PTR3 Function PWM Timer PT3 Run Control PTR3 ‘0’: Timer PT3 is disconnected from its input clock ‘1’: Timer PT3 is running PWM Timer PT3 Input Clock Control PTI3 ‘0’: Timer PT3 is clocked with CPU clock...
Page 189: Interrupt Request Generation
ST10R272L - PWM MODULE PWMCON1 (FF32h / 99h) Reset Value: 0000h PEN3 Function PWM Channel 3 Output Enable Control PEN3 ‘0’: Channel 3 output signal disabled, generate interrupt only ‘1’: Channel 3 output signal enabled PWM Channel 3 Mode Control ‘0’: Channel 3 operates in mode 0 (edge aligned PWM)
Page 190: Pwm Output Signals
10.4 PWM output signals In the ST10R272L, the output signal of the PWM channel 3 (POUT3) is alternate output function on Port 7 pin 3 (P7.3). The output signal of PWM channel 3 is enabled by control bit PEN3 in register PWMCON1.
Page 191: General Purpose Timer Units
ST10R272L - GENERAL PURPOSE TIMER UNITS GENERAL PURPOSE TIMER UNITS The GPT unit is a multi-functional timer/counter structure, used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurement, pulse generation and pulse multiplication.
Page 192 ST10R272L - GENERAL PURPOSE TIMER UNITS All three timers of block GPT1 (T2, T3, T4) can run in 3 basic modes: timer, gated timer, and counter mode, and all timers can count either up or down. Each timer has an associated alternate input function pin on Port 3, which serves as the gate control in gated timer mode, or as the count input in counter mode.
Page 193: 1Gpt1 Core Timer T3
ST10R272L - GENERAL PURPOSE TIMER UNITS 11.1.1 GPT1 core timer T3 The core timer T3 is configured and controlled by its bit addressable control register T3CON. T3CON (FF42h / A1h) Reset Value: 0000h T3OE T3UD Function Timer 3 Input Selection Depends on the operating mode, see respective sections.
Page 194 ST10R272L - GENERAL PURPOSE TIMER UNITS Timer 3 run bit The timer can be started or stopped by software through bit T3R (Timer T3 Run Bit). If T3R=‘0’, the timer stops, T3R= ‘1’ starts the timer. In gated timer mode, the timer will only run if T3R=‘1’ and the gate is active (high or low, as programmed).
Page 195 ST10R272L - GENERAL PURPOSE TIMER UNITS DP3.3 to ‘1’. If T3OE=‘1’, pin T3OUT outputs the state of T3OTL. If T3OE=‘0’, pin T3OUT can be used as general purpose IO pin. T3OTL can also be used in conjunction with the timer over/underflows as an input for the counter function or as a trigger source for the reload function of the auxiliary timers T2 and T4.
Page 196 ST10R272L - GENERAL PURPOSE TIMER UNITS Timer Input Selection T2I / T3I / T4I Pre-scaler factor 1024 Resolution in 1024 CPU clock cycles Table 32 GPT1 timer resolutions Timer 3 in gated timer mode Gated timer mode for the core timer T3 is selected by setting bit field T3M in the T3CON register to ‘010...
Page 197 ST10R272L - GENERAL PURPOSE TIMER UNITS Note A transition of the gate signal at pin T3IN does not cause an interrupt request. x = 3 T3IN = P3.6 T3EUD = P3.4 T3OUT = P3.3 Figure 71 Block diagram of core timer T3 in gated timer mode...
Page 198 ST10R272L - GENERAL PURPOSE TIMER UNITS x = 3 T3IN = P3.6 T3EUD = P3.4 T3OUT = P3.3 Figure 72 Block diagram of core timer T3 in counter mode Triggering Edge for Counter Increment / Decrement 0 0 0 None. Counter T3 is disabled...
Page 199 ST10R272L - GENERAL PURPOSE TIMER UNITS each transition on one or both of the external input pins which gives 2-fold or 4-fold resolution to the encoder input. T3IN edge detect T3IR T3OUT Up/Down T3OTL T3OE T3EUD phase detect T3UD Figure 73 Core timer T3 in incremental interface mode Bitfield T3I in the T3CON control register selects the triggering transitions (see table below).
Page 200 ST10R272L - GENERAL PURPOSE TIMER UNITS The incremental encoder can be connected directly to the ST10R272L without external interface logic. However, in a standard system comparators are employed to convert the encoder’s differential outputs (e.g. A, A) to digital signals (e.g. A). this greatly increases noise immunity.
Page 201 ST10R272L - GENERAL PURPOSE TIMER UNITS In incremental interface mode, the count direction is automatically derived from the sequence in which the input signals change. This corresponds to the rotation direction of the connected sensor. The table below summarizes the possible combinations.
Page 202: 2Gpt1 Auxiliary Timers T2 And T4
ST10R272L - GENERAL PURPOSE TIMER UNITS forward jitter backward jitter forward T3IN T3EUD Contents of T3 down Figure 76 Evaluation of the incremental encoder signals Note Timer 3 operating in incremental interface mode, automatically provides information on the sensor’s current position. Dynamic information (speed, acceleration, deceleration) may be obtained by measuring the incoming signal periods.
Page 203 ST10R272L - GENERAL PURPOSE TIMER UNITS functions which are present in all 3 timers of block GPT1 are controlled in the same bit positions and in the same manner in each of the specific control registers. T2CON (FF40h / A0h)
Page 204 ST10R272L - GENERAL PURPOSE TIMER UNITS Function TxUDE Timer x External Up/Down Enable 1. For the effects of bits TxUD and TxUDE refer to Table 31 GPT1 core timer T3 count direc- tion control. Count direction control for auxiliary timers The count direction of the auxiliary timers can be controlled in the same way as for the core timer T3.
Page 205 ST10R272L - GENERAL PURPOSE TIMER UNITS The event causing an increment or decrement of a timer can be a positive, a negative, or both a positive and a negative transition at either the respective input pin, or at the toggle latch T3OTL.
Page 206 ST10R272L - GENERAL PURPOSE TIMER UNITS core timer T3. This configuration forms a 33-bit timer (16-bit core timer+T3OTL+16-bit auxiliary timer). The count directions of the two concatenated timers are not required to be the same. This offers a wide variety of different configurations.
Page 207 ST10R272L - GENERAL PURPOSE TIMER UNITS Note When programmed for reload mode, the respective auxiliary timer (T2 or T4) stops independent of its run flag T2R or T4R. Note: Line only affected by over/underflows of T3, but NOT by software modifications of T3OTL.
Page 208 ST10R272L - GENERAL PURPOSE TIMER UNITS negative transition of T3OTL. With this combination the core timer is alternately reloaded from the two auxiliary timers. The figure below shows an example for the generation of a PWM signal using the alternate reload mechanism.
Page 209: 3Interrupt Control For Gpt1 Timers
ST10R272L - GENERAL PURPOSE TIMER UNITS Auxiliary timer in capture mode Capture mode for the auxiliary timers T2 and T4 is selected by setting bit field TxM in the respective register TxCON to ‘101 ’. In capture mode the contents of the core timer are latched into an auxiliary timer register in response to a signal transition at the respective auxiliary timer's external input pin TxIN.
Page 210 ST10R272L - GENERAL PURPOSE TIMER UNITS in register TxIC will be set. This will cause an interrupt to the respective timer interrupt vector (T2INT, T3INT or T4INT) or trigger a PEC service, if the respective interrupt enable bit (T2IE, T3IE or T4IE in register TxIC) is set. There is an interrupt control register for each of the three timers.
Page 211: Timer Block Gpt2
ST10R272L - GENERAL PURPOSE TIMER UNITS 11.2 Timer block GPT2 From a programmer’s point of view, the GPT2 block is represented by a set of SFRs as summarized below. Those portions of port and direction registers which are used for alternate functions by the GPT2 block are shaded.
Page 212: 1Gpt2 Core Timer T6
ST10R272L - GENERAL PURPOSE TIMER UNITS T5EUD CPU Clock n=2...9 Interrupt GPT2 Tim er T5 Mode Request T5IN Control Clear Capture Interrupt CAPIN Request GPT2 CAPREL Reload Interrupt Request Toggle FF T6IN Mode T60TL GPT2 Tim er T6 T6OUT CPU Clock Control n=2...9...
Page 213 ST10R272L - GENERAL PURPOSE TIMER UNITS Function Timer 6 Mode Control (Basic Operating Mode) 0 0 0: Timer Mode 0 0 1: Counter Mode 0 1 0: Gated Timer with Gate active low 0 1 1: Gated Timer with Gate active high 1 X X: Reserved.
Page 214 ST10R272L - GENERAL PURPOSE TIMER UNITS 1. For the effects of bits T6UD and T6UDE refer to Table 37 GPT2 core timer T6 count direc- tion control below. Timer 6 run bit The timer can be started or stopped by software through bit T6R (Timer T6 Run Bit). If T6R=‘0’, the timer stops.
Page 215 ST10R272L - GENERAL PURPOSE TIMER UNITS Timer 6 output toggle latch An overflow or underflow of timer T6 will clock the toggle bit T6OTL in control register T6CON. T6OTL can also be set or reset by software. Bit T6OE (Alternate Output Function Enable) in register T6CON enables the state of T6OTL to be an alternate function of the external output pin T6OUT/P3.1.
Page 216 ST10R272L - GENERAL PURPOSE TIMER UNITS resolution r are scaled linearly with lower clock frequencies f , as can be seen from the following formula:. 〈 〉 〈 〉 ⁄ × × ⁄ T6 µS C PU T6EUD = P5.10 x = 6 T6OUT = P3.1...
Page 217 ST10R272L - GENERAL PURPOSE TIMER UNITS Timer 6 in gated timer mode Gated timer mode for the core timer T6 is selected by setting bit field T6M in register T6CON to ‘010 ’ or ‘011 ’. Bit T6M.0 (T6CON.3) selects the active level of the gate input. In gated timer mode the same options for the input frequency as for the timer mode are available.
Page 218: 2Gpt2 Auxiliary Timer T5
ST10R272L - GENERAL PURPOSE TIMER UNITS timer can be a positive, a negative, or both a positive and a negative transition at this pin. Bit field T6I in control register T6CON selects the triggering transition (see table below). The maximum input frequency which is allowed in counter mode is f /8.
Page 219 ST10R272L - GENERAL PURPOSE TIMER UNITS to these 3 counting modes, the auxiliary timer can be concatenated with the core timer. The auxiliary timer has no output toggle latch and no alternate output function. The individual configuration for timer T5 is determined by its bitaddressable control register T5CON.
Page 220 ST10R272L - GENERAL PURPOSE TIMER UNITS Function Timer 5 Capture Mode Enable T5SC T5SC = ‘0’: Capture into register CAPREL Disabled T5SC = ‘1’: Capture into register CAPREL Enabled 1. For the effects of bits TxUD and TxUDE refer to Table 37 GPT2 core timer T6 count direction control.
Page 221 ST10R272L - GENERAL PURPOSE TIMER UNITS The event causing an increment or decrement of the timer can be a positive, a negative, or both a positive and a negative transition at either the input pin, or at the toggle latch T6OTL.
Page 222 ST10R272L - GENERAL PURPOSE TIMER UNITS The count directions of the two concatenated timers are not required to be the same. This offers a wide variety of different configurations. T6 can operate in timer, gated timer or counter mode in this case.
Page 223 ST10R272L - GENERAL PURPOSE TIMER UNITS When a selected transition at the external input pin (CAPIN, T3IN, T3EUD) is detected, the contents of the auxiliary timer T5 are latched into register CAPREL, and interrupt request flag CRIR is set. With the same event, timer T5 can be cleared to 0000 .
Page 224 ST10R272L - GENERAL PURPOSE TIMER UNITS register. However, interrupt request flag T6IR will be set indicating the overflow/underflow of Figure 90 GPT2 register CAPREL in reload mode GPT2 capture/reload register CAPREL in capture-and-reload mode Since the reload function and the capture function of register CAPREL can be enabled individually by bits T5SC and T6SR, the two functions can be enabled simultaneously by setting both bits.
Page 225 ST10R272L - GENERAL PURPOSE TIMER UNITS Figure 91 GPT2 register CAPREL in capture-and-reload mode This combined mode can be used to detect consecutive external events which may occur periodically, but where a finer resolution, that means, more ’ticks’ within the time between two external events is required.
Page 226: 3Interrupt Control For Gpt2 Timers And Caprel
ST10R272L - GENERAL PURPOSE TIMER UNITS The underflow signal of timer T6 can furthermore be used to clock one or more of the timers of the CAPCOM units, which gives the user the possibility to set compare events based on a finer resolution than that of the external events.
Page 227: Asynchronous/Synchronous Serial Interface
ST10R272L - ASYNCHRONOUS/SYNCHRONOUS SERIAL INTERFACE ASYNCHRONOUS/SYNCHRONOUS SERIAL INTERFACE The asynchronous/synchronous serial interface ASC0 provides serial communication between the ST10R272L and other microcontrollers, microprocessors or external peripherals. A dedicated baud rate generator sets up all standard baud rates without oscillator tuning. 3 separate interrupt vectors are provided for transmission, reception and erroneous reception.
Page 228 ST10R272L - ASYNCHRONOUS/SYNCHRONOUS SERIAL INTERFACE The Loop-Back option (selected by bit S0LB) simultaneously receives the data currently being transmitted. This may be used to test serial communication routines at an early stage without having to provide an external network. In loop-back mode the alternate input/output functions of the Port 3 pins are not necessary.
Page 229: Asynchronous Operation
ST10R272L - ASYNCHRONOUS/SYNCHRONOUS SERIAL INTERFACE Function Framing Check Enable Bitasync. operation S0FEN Ignore framing errors Check framing errors Overrun Check Enable Bit S0OEN Ignore overrun errors Check overrun errors Parity Error Flag S0PE Set by hardware on a parity error (S0PEN=’1’). Must be reset by software.
Page 230 ST10R272L - ASYNCHRONOUS/SYNCHRONOUS SERIAL INTERFACE TXD0/P3.10 and received on pin RXD0/P3.11. These signals are alternate functions of Port 3 pins. Figure 92 Asynchronous mode of serial channel ASC0 8-bit data frames either consist of 8 data-bits D7...D0 (S0M=’001b’), or of 7 data-bits D6...D0 plus an automatically generated parity bit (S0M=’011b’).
Page 231 ST10R272L - ASYNCHRONOUS/SYNCHRONOUS SERIAL INTERFACE interrupt request flag, if a wrong parity bit is received. The parity bit itself will be stored in bit S0RBUF.8. In wake-up mode, received frames are only transferred to the receive buffer register if the 9th bit (the wake-up bit) is ‘1’.
Page 232: Synchronous Operation
ST10R272L - ASYNCHRONOUS/SYNCHRONOUS SERIAL INTERFACE • the data field (8 or 9 bits, LSB first, including a parity bit, if selected) • the delimiter (1 or 2 stop bits) Data transmission is double buffered. When the transmitter is idle, the transmit data loaded into S0TBUF is immediately moved to the transmit shift register thus freeing S0TBUF for the next data to be sent.
Page 233 ST10R272L - ASYNCHRONOUS/SYNCHRONOUS SERIAL INTERFACE P3.10 outputs the shift clock. These signals are alternate functions of Port 3 pins. Synchronous mode is selected with S0M=’000b’. 8 data bits are transmitted or received synchronous to a shift clock generated by the internal baud rate generator.
Page 234: Hardware Error Detection Capabilities
ST10R272L - ASYNCHRONOUS/SYNCHRONOUS SERIAL INTERFACE Pin TXD0/P3.10 must be configured for alternate data output, i.e. P3.10=’1’ and DP3.10=’1’, in order to provide the shift clock. Pin RXD0/P3.11 must also be configured for output (P3.11=’1’ and DP3.11=’1’) during transmission. Synchronous reception is initiated by setting bit S0REN=’1’. If bit S0R=1, the data applied at pin RXD0 are clocked into the receive shift register synchronous to the clock which is output at pin TXD0.
Page 235: Asc0 Baud Rate Generation
ST10R272L - ASYNCHRONOUS/SYNCHRONOUS SERIAL INTERFACE the error interrupt request is due to an overrun error (Asynchronous and synchronous mode). 12.4 ASC0 baud rate generation The serial channel ASC0 has its own dedicated 13-bit baud rate generator with 13-bit reload capability, allowing baud rate generation independent from the timers.
Page 236: 2Synchronous Mode Baud Rates
ST10R272L - ASYNCHRONOUS/SYNCHRONOUS SERIAL INTERFACE 12.4.2 Synchronous mode baud rates For synchronous operation, the baud rate generator provides a clock with 4 times the rate of the established baud rate. The baud rate for synchronous operation of serial channel ASC0...
Page 237: Using The Asc0 Interrupts
ST10R272L - ASYNCHRONOUS/SYNCHRONOUS SERIAL INTERFACE Note In contrast to the error interrupt request flag S0EIR, the error status flags S0FE/ S0PE/S0OE are not reset automatically on entry into the error interrupt service routine, but must be cleared by software. S0TIC (FF6Ch / B6h)
Page 238 ST10R272L - ASYNCHRONOUS/SYNCHRONOUS SERIAL INTERFACE While the task of the receive interrupt handler is clear, the transmitter is serviced by two interrupt handlers. This provides advantages for the servicing software. For single transfers it is sufficient to use the transmitter interrupt (S0TIR), which indicates that the previously loaded data has been transmitted, except for the last bit of an asynchronous frame.
Page 239: Synchronous Serial Port
EEPROM, via a three-wire interface similar to the SPI protocol. The interface lines are: • SSPCLK: Serial clock output. Driven by the ST10R272L (master) to the peripheral (slave) which is selected for transfer. • SSPDAT: Bi-directional serial data line. Data is transferred between the ST10R272L and the peripheral at up to 10 MBit/s.
Page 240: Xbus Implementation
ST10R272L - SYNCHRONOUS SERIAL PORT 13.1 XBUS implementation The SSP is implemented as an XPERipheral onto the XBUS in the address range 00EF00h - 00EFFFh, a 256 Byte range (10 byte addresses used). It is connected via a 16-bit demultiplexed bus, without waitstates, allowing word and byte accesses via the CPU or the PEC.
Page 241: 1Ssp Control Register 0 - Sspcon0
ST10R272L - SYNCHRONOUS SERIAL PORT effecting other mechanisms. The figure below shows all control and data registers of the SSP. Data Registers Control Registers Interrupt Control (8-bit registers) SSPTB0 SSPCON0 XP1IC SSPRB SSPCON1 SSPTB SSPTB SSP Transmit Byte 0 Register...
Page 242 ST10R272L - SYNCHRONOUS SERIAL PORT SSPCCON0 (00’EF00h) Reset Value: 0000h SSPSEL SSPCKS Function SSP Clock Rate Selection Baud Rate 000: SSP clock = CPU clock divided by 2 MBit/s. 001: SSP clock = CPU clock divided by 4 MBit/s. 010: SSP clock = CPU clock divided by 8 MBit/s.
Page 243: 2Ssp Control Register 1 - Sspcon1
ST10R272L - SYNCHRONOUS SERIAL PORT Function SSP Busy Flag SSP is idle SSP is busy. SSPBSY The Busy flag is set with the first write into one of the transmit buffers. It is automati- cally cleared after the last bit has been transferred and selected chip select line is switched inactive.
Page 244: 3Ssp Transmit Buffer Registers - Ssptbx
ST10R272L - SYNCHRONOUS SERIAL PORT SSPCON1 (00’EF02h) Reset Value: 0000h CEO1 CEO0 CEP1 CEP0 Function (Operating Mode, SSCEN = ‘1’) SSP Chip Enable Line 0 (SSPCEN0) Polarity Control Bit SSPCEP0 Inactive Chip Enable line is low, active level is high.
Page 245: 4Initialization
ST10R272L - SYNCHRONOUS SERIAL PORT Reserved Byte (00’EF07h) Reset Value: xxh SSPTB2 (00’EF06h) Reset Value: xxh reserved TRANSMIT BYTE 2 SSPTB1 (00’EF05h) Reset Value: xxh SSPTB0 (00’EF04h) Reset Value: xxh TRANSMIT BYTE 1 RECEIVE/TRANSMIT BYTE 0 13.2.4 Initialization After reset, all SSP I/O lines are in high-impedance state. The SSPDAT line is controlled automatically by the SSP, according to the performed read or write operation.
Page 246: 6Performing A Write Operation
ST10R272L - SYNCHRONOUS SERIAL PORT When the programming of the control register SSPCON0 is complete, the transfer is started with a write to transmit buffer SSPTB0, regardless of the type of operation (read or write operation). 13.2.6 Performing a Write Operation If the SPRW bit in register SSPCON0 is reset, a write operation is selected.
Page 247 ST10R272L - SYNCHRONOUS SERIAL PORT SSPCLK Byte 2 Byte 1 Byte 0 16 15 14 SSPDAT SSPCE0, 1 Full Write Full Write Full Write VR02084C Figure 101 Write operation controlled through transmit buffer full signal While SSPTB0 must be the last transmit buffer register written, there are no sequence requirment for writing to the other two SSPTBx registers.
Page 248: 7Chip Enable Lines
ST10R272L - SYNCHRONOUS SERIAL PORT Performing a read operation If the SPRW bit in register SSPCON0 is set, a read operation is selected. During a read operation, first information (command or address information) is transferred from the CPU (master) to the slave peripheral. Then the transfer direction is switched, and information is transferred from the slave to the master.
Page 249: 8Using The Ssp Chip Enable And Clock Lines For Output Functions
ST10R272L - SYNCHRONOUS SERIAL PORT The chip enable lines are selected through the control bits SSPSEL0 and SSPSEL1. Note that these automatic chip enable lines can be extended through normal IO pins, which, however, must be activated and deactivated through software. To avoid conflicts with the automatic chip enable lines, the combination ‘00’...
Page 250 ST10R272L - SYNCHRONOUS SERIAL PORT command followed by an address, and then the data byte at this address is returned to the master. However, if the chip enable line is not deactivated after the EEPROM has transferred the first data byte, the EEPROM automatically increments to the next address location. If now subsequent clock pulses are applied to the device, the content of this next location is transferred to the master, and so on.
Page 251: 10Interrupt Control For The Ssp
ST10R272L - SYNCHRONOUS SERIAL PORT received from the slave is stored in register SSPRB0, and an internal flag RB0_Full is set. Reading SSPRB0 through software clears this flag, and issues the next 8 clock pulses to receive the next byte from the slave device. The time between the transfers depends again on the application;...
Page 252: 11Ssp Input/Output Pins
ST10R272L - SYNCHRONOUS SERIAL PORT XP1IC (F18Eh) ESFR Reset Value: - - 00h XP1IR XP1IE ILVL GLVL Note Refer to “Interrupt control registers” on page 86 for an explanation of the control fields. 13.2.11 SSP input/output pins The SSP is connected to the external world by the following four signals on Port 4:...
Page 253 ST10R272L - SYNCHRONOUS SERIAL PORT is used to specify the SSP address area. Contrary to the BUSCONx/ADDRSELx registers, the XBCON1/XADRS1 registers are mask-programmed, i.e. they are not software programmable. The mask-programming of these registers is: XBCON1: 04BFh XADRS1: 0EF0h The XBCON1 register is organized like the BUSCONx registers except that there is no option for read/write chip selects (bits 14 and 15).
Page 254: 13Visibility Of Accesses To The Ssp
13.2.14 Single chip mode This description does not apply to the ST10R272L ROMless device, and only applies to ST10 devices with internal Flash or ROM. Single chip mode is entered during reset with pin EA tied to a logic high level. The chip will start running in single chip mode without an external bus.
Page 255: 16Accessing The Ssp In Hold Mode
Table 43 SSP visibilty 13.2.16 Accessing the SSP in hold mode When the ST10R272L is placed into hold mode by an external HOLD request, accesses to external memory or peripherals have to wait until the HOLD request is deactivated. SSP accesses, however, can be executed in this mode if bit VISIBLE in register SYSCON is cleared.
Page 256: Watchdog Timer
ST10R272L - WATCHDOG TIMER WATCHDOG TIMER The Watchdog Timer is a fail-safe mechanisms which prevents the controller from malfunctioning over a long period of time. The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed.
Page 257: Watchdog Timer Operation
ST10R272L - WATCHDOG TIMER 14.1 Watchdog timer operation The current count value of the watchdog timer is contained in the watchdog timer register WDT, which is a non-bitaddressable read-only register. The operation of the watchdog timer is controlled by its bitaddressable watchdog timer control register WDTCON. This register specifies the reload value for the high byte of the timer, selects the input clock prescaling factor and provides a flag that indicates a watchdog timer overflow.
Page 258 ST10R272L - WATCHDOG TIMER WDTCON (FFAEh / D7h) Reset Value: 000Xh WDTREL Function Watchdog Timer Input Frequency Selection ‘0’: Input frequency is f WDTIN ‘1’: Input frequency is f / 128 Watchdog Timer Reset Indication Flag WDTR Set by the watchdog timer on an overflow.
Page 259: System Reset
ST10R272L - SYSTEM RESET SYSTEM RESET The internal system reset function initializes the ST10R272L into a defined default state. It is invoked either by asserting a hardware reset signal on pin RSTIN (hardware reset input), upon the execution of the SRST instruction (software reset) or by an overflow of the watchdog timer.
Page 260: Asynchronous Hardware Reset
ST10R272L - SYSTEM RESET EINIT instruction RSTOUT Reset State Machine Clock SRST instruction RSTIN watchdog overflow trigger BDRSTEN Internal Reset Signal Reset Sequence (512 CPU clock cycles) Asynchronous Reset RPD/Vpp RPD/Vpp flash device from/to Exit Powerdown Weak Pulldown Circuit (~ 200 mA) Figure 107 Internal reset circuitry 15.1...
Page 261 ST10R272L - SYSTEM RESET held low until the CPU clock signal is available (about 10...50 ms to allow the on-chip oscillator to stabilize). The input RSTIN provides an internal pullup device equalling a resistor of 50 Kohms to 150 KOhms (the minimum reset time must be determined by the lowest value). The RPD/Vpp pin provides an internal pulldown device that causes the external capacitor C2 to discharge at a typical rate of 200 µA.
Page 262: Synchronous Hardware Reset (Warm Reset)
ST10R272L - SYSTEM RESET 15.2 Synchronous hardware reset (warm reset) A warm synchronous hardware reset is triggered when the reset input signal RSTIN is latched low and the RPD/Vpp pin is high. To ensure the recognition of the RSTIN signal (latching), it must be held low for at least 2 CPU clock cycles.
Page 263 ST10R272L - SYSTEM RESET 2 CPU clock min 6 CPU clock max 512 CPU clock 3 or 4 CPU clock 3) CPU Clock internally pulled low RSTIN RPD/Vpp 200 µA Discharge RPD/Vpp >2V 3.3Voperation, >2.5V 5Voperation: RSTOUT Asynchronous Reset not entered.
Page 264 ST10R272L - SYSTEM RESET 6 CPU clock 2 CPU clock 3 or 4 CPU clock 1) 512 CPU clock CPU Clock internally pulled low RSTIN RPD/Vpp µ A Discharge RPD/Vpp >2V 3.3Voperation, >2.5V 5Voperation: RSTOUT Asynchronous Reset not entered. PORT 0...
Page 265 Figure 111 Minimum external reset circuitry The simplest way to reset the ST10R272L, is to insert a capacitor between RSTIN pin and Vss (C1 in Figure 107 ), plus a capacitor between RPD/Vpp pin and Vss (C2) and a pull-up between RPD/Vpp pin and Vcc.
Page 266 ST10R272L - SYSTEM RESET worst-case discharge time needed for the internal or external oscillator to stabilize. See “Selecting R and C values” on page 300 for the formula to calculate an appropriate value for C. The value for R resistor must not interfere with the discharge current of the internal pulldown device on RPD/Vpp pin.
Page 267: Software Reset
Then the internal reset sequence is started. Note A watchdog reset disregards the configuration of P0L.5...P0L.0, and does not reload RP0H register with PORT0 values The watchdog reset cannot occur while the ST10R272L is in bootstrap loader mode! 266/320...
Page 268: Pins After Reset
15.5 Pins after reset After the reset sequence the different groups of pins of the ST10R272L are activated in different ways depending on their function. Bus and control signals are activated immediately after the reset sequence according to the configuration latched from PORT0, so either external accesses can takes place or the external control signals are inactive.
Page 269: 1Reset Input Pin
1. Current bus cycle is completed or aborted. 2. Switches asynchronously with RSTIN, synchronously upon software or watchdog reset. 3. The reset condition ends here. The ST10R272L starts program execution. 4. Activation of the IO pins is controlled by software.
Page 270: 2Reset Output Pin
ST10R272L - SYSTEM RESET for the 512 CPU clock cycles of the internal reset sequence. After the reset sequence has been completed, the RSTIN input is sampled. When the reset input signal is active at that time, the internal reset signal is prolonged until RSTIN gets inactive, but the reset sequence is not re-triggered.
Page 271: Internal Ram After Reset
15.9 Ports and external bus configuration during reset During the internal reset sequence all of the ST10R272L’s port pins are configured as inputs by clearing the associated direction registers, and their pin drivers are switched to the high impedance state. This ensures that the ST10R272L and external devices will not try to drive the same pin to different levels.
Page 272: Application Specific Initialization Routine
15.10 Application specific initialization routine After the internal reset condition is removed the ST10R272L fetches the first instruction from location 00’0000h, which is the first vector in the trap/interrupt vector table, the reset vector. 4 words (locations 00’0000h through 00’0007h) are provided in this table to start the initialization after reset.
Page 273: 1System Start-Up Configuration
EINIT. 15.10.1 System start-up configuration Although most of the programmable features of the ST10R272L are either selected during the initialization phase or repeatedly during program execution, there are some features that must be selected earlier, because they are used for the first access of the program execution (e.g.
Page 274: 2Emulation Mode
XBUS peripherals by the external bus interface pins in application specific versions of the ST10R272L. This mode is used for special emulator purposes and is of no use in basic ST10R272L devices, so in this case P0L.0 should be held high.
Page 275: 3Adapt Mode
When low during reset, Pin P0L.1 (ADP) selects the adapt mode. In this mode the ST10R272L goes into a passive state, which is similar to its state during reset. The pins of the ST10R272L float to tristate or are deactivated via internal pullup/pulldown devices, as described for the reset state.
Page 276: 6Chip Select Lines
Port 4 are automatically switched to address output mode. Even if not all segment address lines are enabled on Port 4, the ST10R272L internally uses its complete 24-bit addressing mechanism. This allows to restrict the width of the effective address bus, while still deriving CS signals from the complete addresses.
Page 277: Register Set
ST10R272L - REGISTER SET REGISTER SET This section summarizes the ST10R272L registers, and explains the description format which is used in the chapters describing the function and layout of the SFRs. For easy reference the registers are ordered: both by name and hexadecimal address (except for GPRs).
Page 278: General Purpose Registers (Gprs)
ST10R272L - REGISTER SET REG_NAME (A16h / A8h) E/SFR Reset Value: - - * *h bitfield bitfield 16.2 General purpose registers (GPRS) The GPRs form the register bank that the CPU works with. This register bank may be located anywhere within the internal RAM via the Context Pointer (CP). Due to the addressing mechanism, GPR banks can only reside within the internal RAM.
Page 279 ST10R272L - REGISTER SET Physical 8-Bit Reset Name Description Address Address Value (CP) + 26 CPU General Purpose (Word) Register R13 UUUUh (CP) + 28 CPU General Purpose (Word) Register R14 UUUUh (CP) + 30 CPU General Purpose (Word) Register R15...
Page 280: Special Function Registers Ordered By Name
16.3 Special function registers ordered by name The following table lists all ST10R272L SFRs in alphabetical order. Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the Extended SFR-Space (ESFRs) are marked with the letter “E” in column “Physical Address”.
Page 281 ST10R272L - REGISTER SET Physical 8-Bit Reset Name Description Address Address Value CC8IC FF88h EX0IN Interrupt Control Register 0000h CC9IC FF8Ah EX1IN Interrupt Control Register 0000h CC10IC FF8Ch EX2IN Interrupt Control Register 0000h CC11IC FF8Eh EX3IN Interrupt Control Register 0000h...
Page 282 ST10R272L - REGISTER SET Physical 8-Bit Reset Name Description Address Address Value IDCHIP F07Ch Device Identifier Register Refer to Data IDMANUF F07Eh Manufacturer/Process Identifier Register Sheet or Errata IDMEM F07Ah On-chip Memory Identifier Register Sheet for val- IDPROG F078h Programming Voltage Identifier Register...
Page 283 ST10R272L - REGISTER SET Physical 8-Bit Reset Name Description Address Address Value FFC0h Port 2 Register (4 bits) -0--h FFC4h Port 3 Register 0000h FFC8h Port 4 Register (8 bits) FFA2h Port 5 Register (read only) XXXXh FFCCh Port 6 Register (8 bits)
Page 284 ST10R272L - REGISTER SET Physical 8-Bit Reset Name Description Address Address Value RP0H F108h System Start-up Configuration Register (Rd. only) XXh S0BG FEB4h Serial Channel 0 baud rate generator reload reg 0000h S0CON FFB0h Serial Channel 0 Control Register 0000h...
Page 285: Special Function Registers Ordered By Address
2. Bit WDTR indicates a watchdog timer triggered reset. 16.4 Special function registers ordered by address The following table lists all SFRs which are implemented in the ST10R272L ordered by their physical address. Bit-addressable SFRs are marked with the letter “b” in column “Name”. 284/320...
Page 286 ST10R272L - REGISTER SET SFRs within the Extended SFR-Space (ESFRs) are marked with the letter “E” in column “Physical Address”.. Physical 8-Bit Reset Name Description Address Address Value EF00h SSPCON0 SSP Control Register 0 0000h EF02h SSPCON1 SSP Control Register 1...
Page 287 ST10R272L - REGISTER SET Physical 8-Bit Reset Name Description Address Address Value F19Ch S0TBIC Serial Channel 0 transmit buffer interrupt control 0000h F19Eh XP3IC PLL unlock Interrupt Control Register 0000h F1C0h EXICON External Interrupt Control Register 0000h F1C2h ODP2 Port 2 Open Drain Control Register...
Page 288 ST10R272L - REGISTER SET Physical 8-Bit Reset Name Description Address Address Value FE40h GPT1 Timer 2 Register 0000h FE42h GPT1 Timer 3 Register 0000h FE44h GPT1 Timer 4 Register 0000h FE46h GPT2 Timer 5 Register 0000h FE48h GPT2 Timer 6 Register...
Page 289 ST10R272L - REGISTER SET Physical 8-Bit Reset Name Description Address Address Value FF08h IDX0 MAC Unit Address Pointer 0 0000h FF0Ah IDX1 MAC Unit Address Pointer 1 0000h FF0Ch BUSCON0 Bus Configuration Register 0 0XX0h FF0Eh CPU Multiply Divide Control Register...
Page 290 ST10R272L - REGISTER SET Physical 8-Bit Reset Name Description Address Address Value FF6Ah CRIC GPT2 CAPREL Interrupt Control Register 0000h FF6Ch S0TIC Serial Channel 0 Transmit Interrupt Control Regis- 0000h FF6Eh S0RIC Serial Channel 0 Receive Interrupt Control Reg. 0000h...
Page 291: Identification Registers
Table 47 Special functional registers ordered by address 1. The system configuration is selected during reset. 2. Bit WDTR indicates a watchdog timer triggered reset. 16.5 Identification registers The ST10R272L has four Identification registers, mapped in ESFR space. These register contain: • a manufacturer identifier •...
Page 292 ST10R272L - REGISTER SET IDMANUF (F07Eh / 3Fh) ESFR MANUF Function Manufacturer Identifier MANUF 020h: SGS-Thomson Manufacturer (JTAG worldwide normalization). IDCHIP (F07Ch / 3Eh) ESFR CHIPID REVID Function Device Revision Identifier REVID Refer to datasheet for values. Device Identifier CHIPID Refer to datasheet for values.
Page 293 ST10R272L - REGISTER SET IDPROG (F078h / 3Ch) ESFR PROGVPP PROGVDD Function Programming Vdd Voltage Vdd voltage for FLASH devices is calculated using the formula: PROGVDD Vdd = 20 * <PROGVDD> / 256 [V] Refer to datasheet for values. Programming Vpp Voltage...
Page 294: Power Reduction Modes
ST10R272L - POWER REDUCTION MODES POWER REDUCTION MODES The ST10R272L has two power reduction modes - ‘Idle Mode’ and’ Power Down mode’. • Idle Mode: the CPU is stopped, but the peripherals continue operation. Idle Mode can be terminated by any reset or interrupt request.
Page 295 ST10R272L - POWER REDUCTION MODES interrupt system is globally disabled) the CPU immediately resumes normal program execution with the instruction following the IDLE instruction. denied CPU Interrupt Request accepted IDLE instruction Active Idle Mode Mode Executed Denied PEC Request PEC Request...
Page 296 Down mode. Clocking of all internal blocks is stopped, but the contents of the internal RAM are preserved through the V pin supply voltage. The Watchdog Timer is stopped in Power Down mode. The ST10R272L provides two different operating Power Down modes: • Protected Power Down mode, •...
Page 297 ST10R272L - POWER REDUCTION MODES has been saved, the trap routine can set a flag or write a certain bit pattern into specific RAM locations, and then execute the PWRDN instruction. If the NMI pin is still low at this time, Power Down mode will be entered, otherwise program execution continues.
Page 298 ST10R272L - POWER REDUCTION MODES EXICON (F1C0h / E0h) ESFR Reset Value: 0000h EXI3ES EXI2ES EXI1ES EXI0ES Functi External Interrupt x Edge Selection Field (x=3...0) Fast external interrupts disabled: standard mode 0 0: EXxIN pin not taken in account for entering/exiting Power Down mode.
Page 299 ST10R272L - POWER REDUCTION MODES ST10R272L 220 kohms-1Mohm s typical Vpp/RPD 1µF typical Figure 117 External RC Circuit on Vpp/RPD pin for exiting powerdown mode with external interrupt To exit Power Down mode with external interrupt, an EXxIN pin must be asserted for at least 40 ns.
Page 300 ST10R272L - POWER REDUCTION MODES XTAL1 CPU clk internal Powerdown signal External Interrupt External R Action Internal Pullup Action /RPD see note ExitPwrd delay for oscillator/pll (internal) stabilization Note: 2.0V for the 3.3V device and 2.5V for the 5V device...
Page 301 ST10R272L - POWER REDUCTION MODES stop pll stop oscillator enter exit_pwrd PULLUP PowerDown /RPD WEAK PULLDOWN (~ 200 µA) external interrupt reset en_clk_n CPU and Peripherals clocks System clock Figure 119 Simplified Powerdown Exit Circuitry 17.2.4 Selecting R and C values...
Page 302 ST10R272L - POWER REDUCTION MODES • For the 5 volt device, The oscillator needs at least 27.5 ms to stabilize (T = 0.0275 s), is 2.5 V, and I is 200µA. The minimum capacitor value for C is then 2.2 ×...
Page 303 ST10R272L - POWER REDUCTION MODES The table below summarizes the state of all ST10R272L output pins during idle and power down mode Output Pin(s) Idle Mode Power Down Mode RD, WR High High CLKOUT Active High RSTOUT Floating Floating A15...A8 / Float A15...A8...
Page 304 18.2 BCD calculations No direct support for BCD calculations is provided in the ST10R272L. BCD calculations are performed by converting BCD data to binary data, performing the desired calculations using standard data types, and converting the result back to BCD data. Due to the enhanced performance of division instructions binary data is quickly converted to BCD data through division by 10d.
Page 305 18.3 Stack operations The ST10R272L supports two types of stacks. The system stack is used implicitly by the controller and is located in the internal RAM. The user stack provides stack access to the user in either the internal or external memory. Both stack types grow from high memory addresses to low memory addresses.
Page 306 ST10R272L - SYSTEM PROGRAMMING stack is sufficient for the current software and that exceeding its upper or lower boundary represents a fatal error. It is also possible to use the stack underflow and stack overflow traps to cache portions of a larger external stack.
Page 307 ST10R272L - SYSTEM PROGRAMMING Stack Size Internal RAM Addresses (Words) Significant Bits of <STKSZ> (Words) of Physical Stack Stack Pointer SP 0 1 0 b 00’FBFEh...00’FB80h SP.6...SP.0 0 1 1 b 00’FBFEh...00’FBC0h SP.5...SP.0 1 0 0 b Reserved. Do not use this combination.
Page 308 ST10R272L - SYSTEM PROGRAMMING MOV SP, #0F802h ;Set SP before last entry of physical stack of 256 words PUSH R1 ;(SP) = F800h: Physical stack address = FA00h PUSH R2 ;(SP) = F7FEh: Physical stack address = FBFEh The effect of the address transformation, is that the physical stack addresses wraps around - from the end of the defined area to its beginning.
Page 309 18.3.3 Linear stack The ST10R272L offers a linear stack option (STKSZ = ‘111b’), where the system stack may use the complete internal RAM area. This provides a large system stack, without requiring extra procedures to handle data transfers for a circular stack. However, this method also leaves less RAM space for variables or code.
Page 310 ST10R272L - SYSTEM PROGRAMMING bank pointer is then assigned. Therefore, on entry into a new task, the appropriate bank pointer is used as the operand for the SCXT (switch context) instruction. On exit from a task, a simple POP instruction to the context pointer (CP) restores the previous task’s register bank.
Page 311 ST10R272L - SYSTEM PROGRAMMING Note It is possible to use CALLS within the same segment, but still two words of the stack are used to store both the IP and CSP. 18.5.3 Providing local registers for subroutines For subroutines which require local storage, the following methods are provided: Alternate Bank of Registers: Upon entry into a subroutine, it is possible to specify a new set of local registers by executing the SCXT (switch context) instruction.
Page 312 ST10R272L - SYSTEM PROGRAMMING Old Stack Area Old SP Newly Allocated Register Bank New CP New SP Old CP Contents Stack Area Figure 121 Local registers 18.6 Table searching The following features decrease the execution time for table searches. •...
Page 313 All communication between peripherals and the CPU is performed either by PEC transfers to and from internal memory, or by explicitly addressing the SFRs associated with the specific peripherals. After resetting the ST10R272L, all peripherals (except the watchdog timer) are disabled and initialized to default values. The required configuration of a specific peripheral is programmed using MOV instructions of either constants or memory values to specific SFRs.
Page 314 ST10R272L - SYSTEM PROGRAMMING 18.9 Trap/interrupt entry and exit Interrupt routines are entered when a requesting interrupt has a priority higher than the current CPU priority level. Traps are entered regardless of the current CPU priority. When either a trap or interrupt routine is entered, the machine state is preserved on the system stack, and a branch to the appropriate trap/interrupt vector is made.
Page 315 18.12 Short addressing in the extended SFR (ESFR) space The short addressing modes of the ST10R272L (REG or BITOFF) implicitly access the SFR space. Additional ESFR space would have to be accessed by long addressing modes (MEM or [Rw]). The EXTR (extend register) instruction redirects accesses in short addressing modes to the ESFR space for 1...4 instructions.
Page 316 ST10R272L - SYSTEM PROGRAMMING Note Interrupt latencies may be increased when using locked code sequences. PEC requests are not serviced during idle mode, if the IDLE instruction is part of a locked sequence. 315/320...
Page 317 ST10R272L - INDEX OF REGISTERS INDEX OF REGISTERS ADDRSEL1 (FE18h / 0Ch) Reset Value: 0000h - - - - - - - - - - - 168 ADDRSEL2 (FE1Ah / 0Dh) Reset Value: 0000h - - - - - - - - - - - 168...
Page 318 ST10R272L - INDEX OF REGISTERS IDMANUF (F07Eh / 3Fh) ESFR IDMEM (F07Ah / 3Dh) ESFR IDPROG (F078h / 3Ch) ESFR IDX0 (FF08h / 84h) Reset Value: 0000h - - - - - - - - - - - - - 77...
Page 319 ST10R272L - INDEX OF REGISTERS PP3 (F03Eh / 1Fh) ESFR Reset Value: 0000h - - - - - - - - - - - 186 PSW (FF10h / 88h) Reset Value: 0000h - - - - - - - - - - - - 50...
Page 320 ST10R272L - INDEX OF REGISTERS T2IC (FF60h / B0h) Reset Value: - - 00h- - - - - - - - - - - - 209 T3CON (FF42h / A1h) Reset Value: 0000h - - - - - - - - - - - 192...
Page 321 STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics ©2001 STMicroelectronics - All Rights Reserved. Purchase of I C Components by STMicroelectronics conveys a license under the Philips I C Patent.

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