Texas Instruments ADS1282 Manual
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Texas Instruments ADS1282 Manual

High-resolution analog-to-digital converter
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ADS1282 High-Resolution Analog-To-Digital Converter
1 Features
•
High Resolution:
1
130-dB SNR (250 SPS)
•
High Accuracy:
THD: –122 dB
INL: 0.5 ppm
•
Low-Noise PGA
•
Two-Channel Input Mux
•
Inherently-Stable Modulator with Fast Responding
Overrange Detection
•
Flexible Digital Filter:
Sinc + FIR + IIR (Selectable)
Linear or Minimum Phase Response
Programmable High-Pass Filter
Selectable FIR Data Rates: 250 SPS to 4 kSPS
•
Filter Bypass Option
•
Low Power Consumption: 25 mW
Shutdown: 10 μW
•
Offset and Gain Calibration Engine
•
SYNC Input
•
Analog Supply:
Unipolar (+5 V) or Bipolar (±2.5 V)
•
Digital Supply: 1.8 V to 3.3 V
2 Applications
•
Energy Exploration
•
Seismic Monitoring
•
High-Accuracy Instrumentation
Input 1
Input 2
V
COM
Over-Range
Modulator Output
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
Sample &
Product
Buy
Folder
AVDD
VREFN
4th-Order
PGA
DS
Modulator
3
AVSS
Tools &
Technical
Software
Documents
SBAS418I – SEPTEMBER 2007 – REVISED MARCH 2015
3 Description
The ADS1282 is an extremely high-performance,
single-chip analog-to-digital converter (ADC) with an
integrated, low-noise programmable gain amplifier
(PGA) and two-channel input multiplexer (mux). The
ADS1282 is suitable for the demanding needs of
energy
exploration
environments.
The converter uses a fourth-order, inherently stable,
delta-sigma (ΔΣ) modulator that provides outstanding
noise and linearity performance. The modulator is
used either in conjunction with the on-chip digital
filter, or can be bypassed for use with post
processing filters.
The flexible input MUX provides an additional
external input for measurement, as well as internal
self-test connections. The PGA features outstanding
low noise (5 nV/√Hz) and high input impedance,
allowing
easy
hydrophones over a wide range of gains.
The digital filter provides selectable data rates from
250 to 4000 samples per second (SPS). The high-
pass filter (HPF) features an adjustable corner
frequency. On-chip gain and offset scaling registers
support system calibration.
The synchronization input (SYNC) can be used to
synchronize the conversions of multiple ADS1282s.
The SYNC input also accepts a clock input for
continuous alignment of conversions from an external
source.
Together, the amplifier, modulator, and filter dissipate
25 mW. The ADS1282 is available in a compact
TSSOP-28 package and is fully specified from –40°C
to +85°C, with a maximum operating range to
+125°C.
VREFP
DVDD
ADS1282
Programmable
Calibration
Digital Filter
DGND
Support &
Community
and
seismic
interfacing
to
geophones
CLK
SCLK
DOUT
SPI
Interface
DIN
DRDY
SYNC
Control
RESET
PWDN
ADS1282
monitoring
and

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Summary of Contents for Texas Instruments ADS1282

  • Page 1 • Seismic Monitoring • High-Accuracy Instrumentation Together, the amplifier, modulator, and filter dissipate 25 mW. The ADS1282 is available in a compact TSSOP-28 package and is fully specified from –40°C to +85°C, with a maximum operating range to +125°C. AVDD...

  • Page 2: Ordering Information

    SBAS418I – SEPTEMBER 2007 – REVISED MARCH 2015 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

  • Page 3: Electrical Characteristics

    (7) The PGA output impedance and the modulator input impedance results in –1% systematic gain error. (8) Gain match relative to PGA = 1. (9) f is the input common-mode frequency. f is the power-supply frequency. Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: ADS1282...
  • Page 4 /2 (N = 1, 2, 3...) can mix with the modulator chopping clock. In these frequency DATA ranges intermodulation = 120dB, typ. (11) At dc; see Figure (12) CLK input stopped. Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: ADS1282...

  • Page 5: Timing Diagram

    SCDL data. (Also between consecutive commands.) (1) Holding SCLK low for 64 DRDY falling edges resets the serial interface. (2) Load on DOUT = 20pF || 100kΩ. Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: ADS1282...

  • Page 6: Pin Configuration And Functions

    Power-down input, active low RESET Digital input Reset input, active low DVDD Digital supply Digital power supply: +1.8V to +3.3V BYPAS Analog Sub-regulator output: Connect 1μF capacitor to DGND Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: ADS1282...

  • Page 7: Typical Characteristics

    SNR = 124.2dB -100 -120 -140 -160 V = 0.5dBFS -180 100 150 Frequency (Hz) Input Frequency (Hz) Figure 5. Output Spectrum Figure 6. THD vs Input Frequency Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: ADS1282...
  • Page 8 Data Rate = f /4096 V = 20mV Data Rate = f /4096 (MHz) (MHz) Figure 11. SNR vs Clock Frequency Figure 12. THD vs Clock Frequency Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: ADS1282...
  • Page 9 Adjacent Channel V = 0.5dBFS, 31.25Hz 100 150 200 250 300 350 400 450 Frequency (Hz) Temperature ( C) ° Figure 17. Crosstalk Output Spectrum Figure 18. Power vs Temperature Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: ADS1282...
  • Page 10 PGA = 32 PGA = 8, 64 PGA = 16 Gain Drift (ppm/ C) ° Gain Error (%) Figure 23. Gain Drift Histogram Figure 24. Gain Match Histogram Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: ADS1282...
  • Page 11 SBAS418I – SEPTEMBER 2007 – REVISED MARCH 2015 9 Overview The ADS1282 is a high-performance analog-to-digital Gain and offset registers scale the digital filter output converter (ADC) intended for energy exploration, to produce the final code value. The scaling feature...

  • Page 12: Noise Performance

    Equation 9.1 ADS1282H SNR = 20log The H version of the ADS1282 has an improved input stage compared to the base version ADS1282. The where: ADS1282H design is optimized for use with high impedance sensors, such as hydrophones. The /(2 ×...
  • Page 13 Input 2 LOAD addition to internal connections for various self-test modes. Table summarizes multiplexer configurations for Figure Figure 28. Driving an External Load Through the Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: ADS1282...
  • Page 14 9.6 PGA (Programmable Gain Amplifier) PGA (Programmable Gain Amplifier) (continued) The PGA of the ADS1282 is a low-noise, continuous- time, differential-in/differential-out CMOS amplifier. The gain is programmable from 1 to 64, set by register bits, PGA[2:0]. The PGA differentially drives the modulator through 300Ω...
  • Page 15 ADS1282 www.ti.com SBAS418I – SEPTEMBER 2007 – REVISED MARCH 2015 9.7 ADC Modulator (continued) The ADC block of the ADS1282 is composed of two appears at the chopping frequency (f /512 = 8kHz). sections: high-accuracy modulator The component at 5.8kHz is the tone frequency, programmable digital filter.
  • Page 16 Modulator Over-Range (continued) 9.11 Modulator Over-Range Detection (MFLAG) the normal range, the modulator requires up to 12 The ADS1282 has a fast-responding over-range modulator clock cycles (f ) to exit saturation and detection that indicates when the differential input return to the linear region. The digital filter requires an exceeds 100% or –100% full-scale.
  • Page 17 (VREFP, VREFN) The modulator digital stream output is accessible directly, bypassing and disabling the internal digital The voltage reference for the ADS1282 is the filter. The modulator output mode is activated by differential voltage between VREFP and VREFN: setting the CONFIG0 register bits FILTR[1:0] = 00.

  • Page 18: Digital Filter

    SBAS418I – SEPTEMBER 2007 – REVISED MARCH 2015 www.ti.com Digital Filter (continued) The ADS1282 reference inputs are protected by ESD diodes. In order to prevent these diodes from turning Table 5. Digital Filter Selection on, the voltage on either input must stay within the...
  • Page 19 Figure 39 shows the roll-off of the sinc filter. 9.14.2 FIR Stage The second stage of the ADS1282 digital filter is an FIR low-pass filter. Data are supplied to this stage from the sinc filter. The FIR stage is segmented into...
  • Page 20 – f and Nf , where N = 1, 2, etc. and f = passband). These image frequencies, if present in the signal and not externally filtered, fold Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: ADS1282...
  • Page 21 9.15.3 HPF Stage The minimum phase filter provides a short delay from The last stage of the ADS1282 filter block is a first- the arrival of an input signal to the output, but the order HPF implemented as an IIR structure. This filter...
  • Page 22 Group Delay and Step Response (continued) 9.16 Master Clock Input (CLK) The ADS1282 requires a clock input for operation. The HPF causes a small gain error, in which case the The clock is applied to the CLK pin. The data...
  • Page 23 SBAS418I – SEPTEMBER 2007 – REVISED MARCH 2015 9.18 Pulse-Sync Mode Continuous-Sync Mode (continued) In Pulse-sync mode, the ADS1282 stops and restarts Note that a SYNC clock input should be applied after the conversion process when a sync event occurs (by the Continuous-Sync mode is set.

  • Page 24: Power-On Sequence

    Command) (PWDN Pin and Standby Command) (continued) The ADS1282 may be reset in two ways: toggle the RESET pin low or send a Reset command. When In power-down, note that the device outputs remain using the RESET pin, take it low and hold for at least active and the device inputs must not float.

  • Page 25: Serial Interface

    9.24.3 Data Output (DOUT) FPGA or Processor The data output pin (DOUT) is used to output data SCLK from the ADS1282. Data are shifted out on DOUT on SCLK the falling edge of SCLK. DOUT1 DOUT1...

  • Page 26: Data Format

    SBAS418I – SEPTEMBER 2007 – REVISED MARCH 2015 www.ti.com Serial Interface (continued) 9.25 Data Format The ADS1282 provides 32 bits of conversion data in 9.24.4 Data Ready (DRDY) binary twos complement format, as shown in DRDY is an output; when it transitions low, this Table 13.

  • Page 27: Reading Data

    SBAS418I – SEPTEMBER 2007 – REVISED MARCH 2015 9.26 Reading Data Reading Data (continued) The ADS1282 has two ways to read conversion data: When a Stop Read Data Continuous command is Read Data Continuous and Read Data By Command. issued, the DRDY output is blocked but the ADS1282 continues conversions.

  • Page 28: One-Shot Operation

    SBAS418I – SEPTEMBER 2007 – REVISED MARCH 2015 www.ti.com 9.27 One-Shot Operation 9.28 Offset and Full-Scale Calibration Registers The ADS1282 can perform very power-efficient, one- shot conversions using the STANDBY command The conversion data can be scaled for offset and gain while under software control. Figure 58 shows this before yielding the final output code.
  • Page 29 REGISTER BYTE BIT ORDER OFC0 B0 (LSB) OFC1 OFC2 B23 (MSB) Table 19. Full-Scale Calibration Word REGISTER BYTE BIT ORDER FSC0 B0 (LSB) FSC1 FSC2 B23 (MSB) Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: ADS1282...

  • Page 30: Calibration Commands

    (Figure 60), a zero input signal signals must be applied to the ADS1282 inputs must be applied to the ADS1282 and the inputs before sending the commands. Use slower data rates allowed to stabilize. When the command sequence to achieve more consistent calibration results; this...

  • Page 31: User Calibration

    ADS1282 www.ti.com SBAS418I – SEPTEMBER 2007 – REVISED MARCH 2015 9.30 User Calibration User Calibration (continued) System calibration of the ADS1282 can be performed The value written to the FSC registers is calculated without using calibration commands. This Equation procedure requires the calibration values to be...
  • Page 32 The commands listed in Table 20 control the In Read Data Continuous mode, the ADS1282 places operation of the ADS1282. Most commands are conversion data on the DOUT pin as SCLK is stand-alone (that is, 1 byte in length); the register applied.
  • Page 33 Read Data Continuous method with DIN held low. conversions. STANDBY: Standby Mode RDATA: Read Data by Command Description: This command places the ADS1282 Description: This command reads the conversion into Standby mode. In Standby, the device enters a data. See the...
  • Page 34 Command Byte 1 = 0100 0101 Command Byte 2 = 0000 0101 Figure 64. Write Register Data (Table 21 Shows t Table 21. t Value PARAMETER 24/f Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: ADS1282...

  • Page 35: Register Map

    FSC19 FSC18 FSC17 FSC16 Table 23. ID : ID Register (Address 00h) Reset value = X0h. Bit[7:4] ID[3:0] Factory-programmed identification bits (read-only) Bit[3:0] Reserved Always write '0' Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: ADS1282...
  • Page 36 00: On-chip filter bypassed, modulator output mode 01: Sinc filter block only 10: Sinc + LPF filter blocks (default) 11: Sinc + LPF + HPF filter blocks Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: ADS1282...
  • Page 37 000: G = 1 (default) 001: G = 2 010: G = 4 011: G = 8 100: G = 16 101: G = 32 110: G = 64 Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: ADS1282...
  • Page 38 FSC09 FSC08 Reset value = 00h. Table 33. FSC2: Full-Scale Calibration, High Byte (Address 0ah) FSC23 FSC22 FSC21 FSC20 FSC19 FSC18 FSC17 FSC16 Reset value = 40h. Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: ADS1282...

  • Page 39: Configuration Guide

    (undefined I/O power-up 5. Synchronize readings. Whenever SYNC is high, sequencing may cause false SCLK detection). To the ADS1282 freely runs the data conversions. reset the SPI interface, toggle the RESET pin or, To stop and re-sync the conversions, take SYNC when in Read Data Continuous mode, hold SCLK low and then high.

  • Page 40: Application Information

    The REF02 +5V reference provides the reference to away from converter front-end the ADS1282. The reference output is filtered by the components. Locating the digital components close to optional R and C filter network. The filter requires the power-entry point keeps the digital current path several seconds to settle after power-on.
  • Page 41 VREFN DGND -2.5V 6, 12, 25, 27 (1) Optional 20mV offset. Match to 0.1% to maintain CMR. (2) Optional external diode clamps. Figure 65. Geophone Interface Application Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: ADS1282...
  • Page 42 ADS1282s are shown connected. The the digital inputs. 47Ω resistors in series with the DRDY output from each ADS1282 can be used; digital traces can help to reduce ringing by controlling however, when the devices are synchronized, the impedances.
  • Page 43 –125456 –1300087 2351253 893263 –122207 –878642 –3357202 580196 –61813 1162189 –3767666 224751 –4445 1741565 1087392 –18203 22484 –522533 3847821 –118690 22245 –2490395 919792 –120064 10775 –688945 –2918303 Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: ADS1282...
  • Page 44 15644 366118 –71728 –693209 –36319 –588382 38331 283878 38783 580424 –13557 34715 –31453 –430178 –1230 –215231 20983 231231 7729 263758 –11463 –56082 –8791 –220104 4659 –56626 7126 Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: ADS1282...
  • Page 45 –976 –94192 2551 –7546 1339 61387 –1103 33460 –1085 –25549 –34123 22008 –349 10620 –96 –8280 –10663 –266 –46 7419 –42 6692 2481 –75 –432 –4 –132 Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: ADS1282...
  • Page 46 = number of CLK cycles from next rising CLK edge directly after eighth rising SCLK edge to DRDY falling edge. For Wake-Up command only, subtract two f cycles. Table 35 is referenced by Table 10 Table Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: ADS1282...

  • Page 47: Revision History

    468/f in t row of Table 10 ......................• Updated Figure 65, showing alternate bias resistor location....................• Corrected Table 34 (Appendix, FIR Stage Coefficients) ...................... Submit Documentation Feedback Copyright © 2007–2015, Texas Instruments Incorporated Product Folder Links: ADS1282...

  • Page 48: Packaging Information

    CU NIPDAU Level-1-260C-UNLIM -40 to 85 ADS1282HI & no Sb/Br) ADS1282IPW ACTIVE TSSOP Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 ADS1282 & no Sb/Br) ADS1282IPWR ACTIVE TSSOP 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 ADS1282 & no Sb/Br) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
  • Page 49 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF ADS1282 : •...

  • Page 50: Tape And Reel Information

    PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Reel Reel Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1 (mm) ADS1282HIPWR TSSOP 2000 330.0 16.4 10.2 12.0 16.0 ADS1282IPWR TSSOP...
  • Page 51 PACKAGE MATERIALS INFORMATION www.ti.com 26-Feb-2019 *All dimensions are nominal Device Package Type Package Drawing Pins Length (mm) Width (mm) Height (mm) ADS1282HIPWR TSSOP 2000 350.0 350.0 43.0 ADS1282IPWR TSSOP 2000 350.0 350.0 43.0 Pack Materials-Page 2...
  • Page 54 TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2019, Texas Instruments Incorporated...

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