Texas Instruments MSP430 series Manual

Texas Instruments MSP430 series Manual

Mixed signal microcontroller
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FEATURES
1
• Low Supply-Voltage Range, 1.8 V to 3.6 V
23
Ultra-Low Power Consumption
– Active Mode: 270 µA at 1 MHz, 2.2 V
– Standby Mode (VLO): 0.3 µA
– Off Mode (RAM Retention): 0.1 µA
Ultra-Fast Wake-Up From Standby Mode in
Less Than 1 µs
16-Bit RISC Architecture, 62.5-ns Instruction
Cycle Time
Basic Clock Module Configurations:
– Internal Frequencies up to 16 MHz
– Internal Very Low-Power LF Oscillator
– 32-kHz Crystal
– Internal Frequencies up to 16 MHz With
Four Calibrated Frequencies to ±1%
– Resonator
– External Digital Clock Source
– External Resistor
12-Bit Analog-to-Digital (A/D) Converter With
Internal Reference, Sample-and-Hold, and
Autoscan Feature
16-Bit Timer_A With Three Capture/Compare
Registers
16-Bit Timer_B With Seven Capture/Compare
With Shadow Registers
Four Universal Serial Communication
Interfaces (USCI)
– USCI_A0 and USCI_A1
– Enhanced UART Supporting Auto-Baudrate
Detection
– IrDA Encoder and Decoder
– Synchronous SPI
– USCI_B0 and USCI_B1
2
– I
C™
– Synchronous SPI
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
MSP430 is a trademark of Texas Instruments.
2
All other trademarks are the property of their respective owners.
3
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
MIXED SIGNAL MICROCONTROLLER
SLAS547I – JUNE 2007 – REVISED DECEMBER 2012
On-Chip Comparator
Supply Voltage Supervisor/Monitor With
Programmable Level Detection
Brownout Detector
Bootstrap Loader
Serial Onboard Programming, No External
Programming Voltage Needed, Programmable
Code Protection by Security Fuse
Family Members Include:
– MSP430F233
– 8KB+256B Flash Memory,
– 1KB RAM
– MSP430F235
– 16KB+256B Flash Memory
– 2KB RAM
– MSP430F247, MSP430F2471
– 32KB+256B Flash Memory
– 4KB RAM
– MSP430F248, MSP430F2481
– 48KB+256B Flash Memory
– 4KB RAM
– MSP430F249, MSP430F2491
– 60KB+256B Flash Memory
– 2KB RAM
– MSP430F2410
– 56KB+256B Flash Memory
– 4KB RAM
Available in 64-Pin QFP and 64-Pin QFN
Packages (See Available Options)
For Complete Module Descriptions, See
MSP430x2xx Family User's Guide (SLAU144)
(1) The MSP430F24x1 devices are identical to the MSP430F24x
devices, with the exception that the ADC12 module is not
implemented on the MSP430F24x1.
Copyright © 2007–2012, Texas Instruments Incorporated
MSP430F23x
MSP430F24x(1)
MSP430F2410
(1)

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Summary of Contents for Texas Instruments MSP430 series

  • Page 1 MSP430F24x1. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. MSP430 is a trademark of Texas Instruments.
  • Page 2 SLAS547I – JUNE 2007 – REVISED DECEMBER 2012 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
  • Page 3 P6.3/A3 P5.3 P6.4/A4 P5.2 P6.5/A5 P5.1 P6.6/A6 P5.0 P6.7/A7/SVSIN P4.7/TBCLK P4.6 REF+ P4.5 MSP430F23x XOUT P4.4 P4.3 REF+ P4.2/TB2 REF- REF- P1.0/TACLK/CAOUT P4.1/TB1 P1.1/TA0 P4.0/TB0 P1.2/TA1 P3.7 P1.3/TA2 P3.6 P1.4/SMCLK P3.5/UCA0RXD/UCA0SOMI Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 4: P6.3/A3

    P5.3/UCB1CLK/UCA1STE P6.4/A4 P5.2/UCB1SOMI/UCB1SCL P6.5/A5 P5.1/UCB1SIMO/UCB1SDA P6.6/A6 P5.0/UCB1STE/UCA1CLK P6.7/A7/SVSIN P4.7/TBCLK P4.6/TB6 REF+ P4.5/TB5 MSP430F2410, MSP430F24x XOUT P4.4/TB4 P4.3/TB3 REF+ P4.2/TB2 REF- REF- P1.0/TACLK/CAOUT P4.1/TB1 P1.1/TA0 P4.0/TB0 P1.2/TA1 P3.7/UCA1RXD/UCA1SOMI P1.3/TA2 P3.6/UCA1TXD/UCA1SIMO P1.4/SMCLK P3.5/UCA0RXD/UCA0SOMI Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 5: Table Of Contents

    (TOP VIEW) P5.4/MCLK P6.3 P5.3/UCB1CLK/UCA1STE P6.4 P5.2/UCB1SOMI/UCB1SCL P6.5 P5.1/UCB1SIMO/UCB1SDA P6.6 P5.0/UCB1STE/UCA1CLK P6.7/A7/SVSIN P4.7/TBCLK P4.6/TB6 REF+ P4.5/TB5 MSP430F24x1 XOUT P4.4/TB4 P4.3/TB3 P4.2/TB2 P1.0/TACLK/CAOUT P4.1/TB1 P1.1/TA0 P4.0/TB0 P1.2/TA1 P3.7/UCA1RXD/UCA1SOMI P1.3/TA2 P3.6/UCA1TXD/UCA1SIMO P1.4/SMCLK P3.5/UCA0RXD/UCA0SOMI Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 6 Timer_B3 USCI A0 Multiplier UART/LIN, Timer_A3 Watchdog 3 CC IrDA, SPI WDT+ JTAG MPY, Registers, Comp_A+ 3 CC Interface SVS/SVM MPYS, Shadow USCI B0 Registers 15/16-Bit MAC, SPI, I2C MACS RST/NMI Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 7: Xout

    Watchdog 7 CC IrDA, SPI IrDA, SPI WDT+ JTAG MPY, Registers, Comp_A+ 3 CC Interface SVS/SVM MPYS, Shadow USCI B0 USCI B1 Registers 15/16-Bit MAC, SPI, I2C SPI, I2C MACS RST/NMI Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 8 Watchdog 7 CC IrDA, SPI IrDA, SPI WDT+ JTAG MPY, Registers, Comp_A+ 3 CC Interface SVS/SVM MPYS, Shadow USCI B0 USCI B1 Registers 15/16-Bit MAC, SPI, I2C SPI, I2C MACS RST/NMI Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 9: P1.0/Taclk/Caout

    General-purpose digital I/O / analog input A0 - 12-bit ADC P6.1/A1 General-purpose digital I/O / analog input A1 - 12-bit ADC P6.2/A2 General-purpose digital I/O / analog input A2 - 12-bit ADC Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 10: P6.4/A4

    Input for crystal oscillator XT1. Standard or watch crystals can be connected. XOUT Output for crystal oscillator XT1. Standard or watch crystals can be connected. QFN Pad QFN package pad connection to DV recommended Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 11: P1.1/Ta0

    General-purpose digital I/O / switch all PWM digital output ports to high impedance - Timer_B TB0 to P5.7/TBOUTH/SVSOUT TB6/SVS comparator output P6.0/A0 General-purpose digital I/O / analog input A0 - 12-bit ADC Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 12: P6.5/A5

    Input for crystal oscillator XT1. Standard or watch crystals can be connected. XOUT Output for crystal oscillator XT1. Standard or watch crystals can be connected. QFN Pad QFN package pad connection to DV recommended (RGC package only) Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 13: P1.2/Ta1

    General-purpose digital I/O / auxiliary clock ACLK output General-purpose digital I/O / switch all PWM digital output ports to high impedance - Timer_B TB0 to P5.7/TBOUTH/SVSOUT TB6/SVS comparator output P6.0 General-purpose digital I/O Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 14 Input for crystal oscillator XT1. Standard or watch crystals can be connected. XOUT Output for crystal oscillator XT1. Standard or watch crystals can be connected. QFN Pad QFN package pad connection to DV recommended (RGC package only) Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 15 M(R10) → R11 Indirect autoincrement ✓ MOV @Rn+,Rm MOV @R10+,R11 R10 + 2 → R10 Immediate ✓ MOV #X,TONI MOV #45,TONI #45 → M(TONI) (1) S = source (2) D = destination Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 16 – ACLK remains active. • Low-power mode 4 (LPM4) – CPU is disabled. – ACLK is disabled. – MCLK and SMCLK are disabled. – DCO dc-generator is disabled. – Crystal oscillator is stopped. Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 17 (10) The interrupt vectors at addresses 0xFFDE to 0xFFC0 are not used in this device and can be used for regular program code if necessary. Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 18 Table 11. Interrupt Flag Register 2 Address UCB0TXIFG UCB0RXIFG UCA0TXIFG UCA0RXIFG rw-1 rw-0 rw-1 rw-0 UCA0RXIFG USCI_A0 receive-interrupt flag UCA0TXIFG USCI_A0 transmit-interrupt flag UCB0RXIFG USCI_B0 receive-interrupt flag UCB0TXIFG USCI_B0 transmit-interrupt flag Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 19 CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include: • Flash memory has n segments of main memory and four segments of information memory (A to D) of Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 20 Segment A contains calibration data. After reset, segment A is protected against programming and erasing. It can be unlocked, but care should be taken not to erase this segment if the device-specific calibration data is required. Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 21 The user must ensure that the default DCO settings are not changed until V CC(min) reaches V . If desired, the SVS circuit can be used to determine when V reaches V CC(min) CC(min) Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 22 18 - P1.6 CCR1 23 - P2.3 ADC12 (internal) 15 - P1.3 CCI2A 15 - P1.3 ACLK (internal) CCI2B 19 - P1.7 CCR2 24 - P2.4 (1) Not available in the MSP430F24x1 devices. Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 23 41 - P4.5 41 - P4.5 CCI5B CCR5 42 - P4.6 CCI6A 42 - P4.6 ACLK (internal) CCI6B CCR6 (1) Not available in the MSP430F24x1 devices. (2) Not available in the MSP430F24x1 devices. Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 24 16-word conversion-and-control buffer. The conversion- and-control buffer allows up to 16 independent ADC samples to be converted and stored without any CPU intervention. Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 25 0x0086 ADC memory-control register5 ADC12MCTL5 0x0085 ADC memory-control register4 ADC12MCTL4 0x0084 ADC memory-control register3 ADC12MCTL3 0x0083 ADC memory-control register2 ADC12MCTL2 0x0082 ADC memory-control register1 ADC12MCTL1 0x0081 ADC memory-control register0 ADC12MCTL0 0x0080 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 26 0x013E Result high word RESHI 0x013C Result low word RESLO 0x013A Second operand 0x0138 Multiply signed + accumulate/operand1 MACS 0x0136 Multiply + accumulate/operand1 0x0134 Multiply signed/operand1 MPYS 0x0132 Multiply unsigned/operand1 0x0130 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 27 USCI B0 baud rate control 0 UCB0BR0 0x006A USCI B0 control 1 UCB0CTL1 0x0069 USCI B0 control 0 UCB0CTL0 0x0068 USCI B0 I2C slave address UCB0SA 0x011A USCI B0 I2C own address UCB0OA 0x0118 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 28 Port P5 input P5IN 0x0030 Port P4 Port P4 resistor enable P4REN 0x0011 Port P4 selection P4SEL 0x001F Port P4 direction P4DIR 0x001E Port P4 output P4OUT 0x001D Port P4 input P4IN 0x001C Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 29 0x0022 Port P1 output P1OUT 0x0021 Port P1 input P1IN 0x0020 Special Functions SFR interrupt flag2 IFG2 0x0003 SFR interrupt flag1 IFG1 0x0002 SFR interrupt enable2 0x0001 SFR interrupt enable1 0x0000 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 30 3.3 V 3.6 V Supply Voltage −V NOTE: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum V of 2.2 V. Figure 1. Operating Area Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 31 (2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external load capacitance is chosen to closely match the required 9 pF. Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 32 = 3 V = 85 °C = 25 °C = 1 MHz = 2.2 V 12.0 16.0 − Supply Voltage − V − DCO Frequency − MHz Figure 2. Figure 3. Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 33 (3) Current for Brownout and WDT+ is included. The WDT+ is clocked by SMCLK. (4) Current for Brownout and WDT+ is included. The WDT+ is clocked by ACLK. (5) Current for Brownout is included. Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 34 LPM4 CURRENT TEMPERATURE 10.0 = 3.6 V = 3 V Vcc = 2.2V Vcc = 1.8 V −40.0 −20.0 0.0 20.0 40.0 60.0 80.0 100.0 120.0 − Temperature − °C Figure 4. Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 35 (unless otherwise noted) PARAMETER TEST CONDITIONS UNIT Low-level input voltage 2.2 V, 3 V + 0.6 High-level input voltage 2.2 V, 3 V 0.8 V Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 36 The output is connected to the center tap of the divider. (2) The output voltage reaches at least 10% and 90% V at the specified toggle frequency. Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 37 −20.0 −15.0 −30.0 = 85°C = 85°C −20.0 −40.0 = 25°C = 25°C −25.0 −50.0 − High-Level Output Voltage − V − High-Level Output Voltage − V Figure 7. Figure 8. Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 38: Msp430F23X

    , where V is the minimum supply voltage for the desired operating frequency. CC(min) CC(min) V CC V hys(B_IT−) V (B_IT−) CC(start) t d(BOR) Figure 9. POR/Brownout Reset (BOR) vs Supply Voltage Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 39: Slas547I – June 2007 – Revised December

    Typical Conditions V CC(drop) 0.001 1000 − Pulse Width − µs − Pulse Width − µs Figure 11. V Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal CC(drop) Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 40 2 and 15. The overdrive is assumed to be > 50 mV. (2) The recommended operating voltage range is limited to 3.6 V. (3) The current consumption of the SVS module is not included in the I current consumption data. Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 41 − Pulse Width − µs V CC(min) t − Pulse Width − µs Figure 13. V : Square Voltage Drop and Triangle Voltage Drop to Generate an SVS Signal (VLD = 1) CC(min) Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 42 DCO(RSEL+1,DCO) DCO(RSEL,DCO) RSEL and RSEL+1 Frequency step between tap DCO 2.2 V, 3 V 1.05 1.08 1.12 ratio DCO(RSEL,DCO+1) DCO(RSEL,DCO) and DCO+1 Duty cycle Measured at P1.4/SMCLK 2.2 V, 3 V Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 43 CAL(12MHz) Gating time: 5 ms 3.6 V 11.64 12.36 BCSCTL1 = CALBC1_16MHZ, 15.52 16.48 16-MHz calibration value DCOCTL = CALDCO_16MHZ, 0°C to 85°C CAL(16MHz) 3.6 V 16.48 Gating time: 2 ms Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 44 11.4 12.6 CAL(12MHz) calibration value Gating time: 5 ms BCSCTL1 = CALBC1_16MHZ, 16-MHz DCOCTL = CALDCO_16MHZ, -40°C to 105°C 3 V to 3.6 V CAL(16MHz) calibration value Gating time: 2 ms Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 45 = 85 °C 11.9 = 85 °C = 105 °C 15.7 = 105 °C 11.7 15.6 11.5 15.5 − Supply Voltage − V − Supply Voltage − V Figure 16. Figure 17. Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 46 Typical Characteristics - DCO Clock Wake-Up Time From LPM3/4 CLOCK WAKE-UP TIME FROM LPM3 DCO FREQUENCY 10.00 RSELx = 0 to 11 1.00 RSELx = 12 to 15 0.10 0.10 1.00 10.00 DCO Frequency − MHz Figure 18. Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 47 0.75 0.75 0.50 0.50 = 1M = 1M 0.25 0.25 0.00 0.00 −50.0 −25.0 25.0 50.0 75.0 100.0 − Temperature − C − Supply Voltage − V Figure 21. Figure 22. Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 48 T version: (MAX(-40 to 105°C) - MIN(-40 to 105°C))/MIN(-40 to 105°C)/(105°C - (-40°C)) (2) Calculated using the box method: (MAX(1.8 to 3.6 V) - MIN(1.8 to 3.6 V))/MIN(1.8 to 3.6 V)/(3.6 V - 1.8 V) Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 49 (4) Frequencies below the MIN specification set the fault flag, frequencies above the MAX specification do not set the fault flag, and frequencies in between might set the flag. (5) Measured with logic-level input frequency, but also applies to operation with crystals. Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 50 LFXT1Sx = 2 1300.0 1200.0 1100.0 1000.0 900.0 800.0 700.0 600.0 500.0 400.0 300.0 LFXT1Sx = 1 200.0 100.0 LFXT1Sx = 0 12.0 16.0 20.0 Crystal Frequency − MHz Figure 24. Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 51 (4) Frequencies below the MIN specification set the fault flag, frequencies above the MAX specification do not set the fault flag, and frequencies in between might set the flag. (5) Measured with logic-level input frequency, but also applies to operation with crystals. Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 52 XT2Sx = 2 1300.0 1200.0 1100.0 1000.0 900.0 800.0 700.0 600.0 500.0 400.0 300.0 XT2Sx = 1 200.0 100.0 XT2Sx = 0 12.0 16.0 20.0 Crystal Frequency − MHz Figure 26. Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 53 TEST CONDITIONS UNIT Internal: SMCLK, ACLK 2.2 V Timer_B clock frequency External: TACLK, INCLK Duty cycle = 50% ± 10% Timer_B capture timing TB0, TB1, TB2 2.2 V, 3 V TB,cap Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 54 (1) f = 1/2t with t ≥ max(t UCxCLK LO/HI LO/HI VALID,MO(Master) SU,SI(USCI) SU,MI(Master) VALID,SO(USCI) For the master's parameters t and t see the SPI parameters of the attached slave. SU,MI(Master) VALID,MO(Master) Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 55 Figure 27. SPI Master Mode, CKPH = 0 1/f UCxCLK CKPL=0 UCLK CKPL=1 t LO/HI t LO/HI t HD,MI t SU,MI SOMI t VALID,MO SIMO Figure 28. SPI Master Mode, CKPH = 1 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 56 STE,LAG 1/f UCxCLK CKPL=0 UCLK CKPL=1 t LO/HI t LO/HI t HD,SI t SU,SI SIMO t STE,ACC t VALID,SO t STE,DIS SOMI Figure 30. SPI Slave Mode, CKPH = 1 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 57 2.2 V Pulse width of spikes suppressed by input filter t HD,STA t SU,STA t HD,STA 1/f SCL t SP t SU,DAT t SU,STO t HD,DAT Figure 31. I C Mode Timing Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 58 (3) The response time is measured at P2.2/CAOUT/TA0/CA4 with an input voltage step, with Comparator_A+ already enabled (CAON = 1). If CAON is set at the same time, a settling time of up to 300 ns is added to the response time. Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 59 400 mV (response) Figure 33. Comparator_A+ Overdrive Definition Figure 34. Comparator_A+ Short Resistance Test Condition CASHORT = 10µA V IN Comparator_A+ − CASHORT = 1 Figure 35. Comparator_A+ Short Resistance Test Condition Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 60 = 3 V (RefVT) Figure 36. Figure 37. SHORT RESISTANCE 100.00 = 1.8 V = 2.2V = 3 V 10.00 = 3.6 V 1.00 − Normalized Input Voltage − V/V Figure 38. Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 61: P6.4

    (3) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced accuracy requirements. (4) The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with reduced accuracy requirements. Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 62 µF REFON VREF+ VREF+ 10 µF 1 µF 10 ms 1 ms 100 ms REFON Figure 39. Typical Settling Time of Internal Reference t vs External Capacitor on V REFON REF+ Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 63 − 10 µ F 100 nF Reference Is Internally REF− eREF− Switched to AV Figure 41. Supply Voltage and Reference Voltage Design V = AV , Internally Connected REF– eREF– Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 64 VREF+ Total unadjusted -– V )min ≤ (V –V eREF+ REF– eREF– eREF+ REF– eREF– 2.2 V, 3 V ±2 ±5 error = 10 µF (tantalum) and 100 nF (ceramic) VREF+ Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 65 (5) No additional current is needed. The V is used during sampling. (6) The on-time t is included in the sampling time t , no additional on time is needed. VMID(on) VMID(sample) Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 66 Supply current into TEST during fuse blow Time to blow fuse (1) Once the fuse is blown, no further access to the JTAG/Test, Spy-Bi-Wire, and emulation feature is possible, and JTAG is switched to bypass mode. Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 67 P1DIR.x Direction 0: Input 1: Output P1OUT.x Module X OUT P1.0/TACLK P1.1/TA0 P1.2/TA1 P1SEL.x P1.3/TA2 P1.4/SMCLK P1IN.x P1.5/TA0 P1.6/TA1 P1.7/TA2 Module X IN P1IE.x P1IRQ.x P1IFG.x P1SEL.x Interrupt Edge Select P1IES.x Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 68 P1.4 (I/O) I: 0; O: 1 P1.4/SMCLK SMCLK P1.5 (I/O) I: 0; O: 1 P1.5/TA0 Timer_A3.TA0 P1.6 (I/O) I: 0; O: 1 P1.6/TA1 Timer_A3.TA1 P1.7 (I/O) I: 0; O: 1 P1.7/TA2 Timer_A3.TA2 Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 69 P2DIR.x Direction 0: Input 1: Output P2OUT.x Module X OUT P2.0/ACLK/CA2 P2.1/TAINCLK/CA3 P2.2/CAOUT/TA0/CA4 P2SEL.x Keeper P2.3/CA0/TA1 P2.4/CA1/TA2 P2IN.x P2.6/ADC12CLK/CA6 P2.7/TA0/CA7 Module X IN P2IE.x P2IRQ.x P2IFG.x P2SEL.x Interrupt Edge Select P2IES.x Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 70 I: 0; O: 1 P2.4/CA1/TA2 Timer_A3.TA2 P2.6 (I/O) I: 0; O: 1 P2.6/ADC12CLK /CA6 ADC12CLK P2.7 (I/O) I: 0; O: 1 P2.7/TA0/CA7 Timer_A3.TA0 (1) X = Don't care (2) MSP430F24x and MSP430F23x devices only Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 71 Table 22. Port P2.5 Pin Functions CONTROL BITS / SIGNALS PIN NAME (P2.x) FUNCTION CAPD DCOR P2DIR.5 P2SEL.5 P2.5 (I/O) I: 0; O: 1 P2.5/R /CA5 1 or selected (1) X = Don't care Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 72 3-wire SPI mode if 4-wire SPI mode is selected. (4) If I C functionality is selected, the output drives only the logical 0 to V level. (5) MSP430F24x and MSP430F24x1 devices only Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 73 I: 0; O: 1 P4.5/TB5 Timer_B7.CCI5A and Timer_B7.CCI5B Timer_B7.TB5 P4.6 (I/O) I: 0; O: 1 P4.6/TB6 Timer_B7.CCI6A and Timer_B7.CCI6B Timer_B7.TB6 P4.7 (I/O) I: 0; O: 1 P4.7/TBCLK Timer_B7.TBCLK (1) MSP430F24x and MSP430F24x1 devices only Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 74 (4) UCA0CLK function takes precedence over UCB0STE function. If the pin is required as UCA0CLK input or output, USCI A/B0 is forced to 3-wire SPI mode if 4-wire SPI mode is selected. (5) If I C functionality is selected, the output drives only the logical 0 to V level. Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 75 I: 0; O: 1 P5.4/MCLK MCLK P5.5 (I/O) I: 0; O: 1 P5.5/SMCLK SMCLK P5.6 (I/O) I: 0; O: 1 P5.6/ACLK ACLK P5.7 (I/O) I: 0; O: 1 P5.7/TBOUTH/SVSOUT Timer_B7.TBOUTH SVSOUT Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 76 P5.4 (I/O) I: 0; O: 1 P6.4/A4 P5.5 (I/O) I: 0; O: 1 P6.5/A5 P6.6 (I/O) I: 0; O: 1 P6.6/A6 (1) X = Don't care (2) MSP430F24x and MSP430F23x devices only Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 77 PIN NAME (P6.x) FUNCTION P6DIR.x P6SEL.x INCHy P6.7 (I/O) I: 0; O: 1 P6.7/A7/SVSIN 1 (y = 7) SVSIN (VLD = 15) (1) X = Don't care (2) MSP430F24x and MSP430F23x devices only Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 78 Burn & T est Fuse Test TDI/TCLK Emulation Module During Programming Activity and During Blowing of the Fuse, Pin TDO/TDI Is Used to Apply the Test Input Data for JTAG Circuitry Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 79 The CODE and RAM data protection is ensured if the JTAG fuse is blown and the 256-bit bootloader access key is used. Also, see the Bootstrap Loader section for more information. Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 80 LPM0,1MHz LPM0,100kHz Corrected number of capture/compare registers in description in Timer_B3 (MSP430F23x Devices). SLAS547I Added typical test conditions in Recommended Operating Conditions. Removed "Timer_A3.CCIxA" entries from P1.5 through P1.7 in Table Submit Documentation Feedback Copyright © 2007–2012, Texas Instruments Incorporated...
  • Page 81 PACKAGE OPTION ADDENDUM www.ti.com 16-Nov-2013 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples Drawing (4/5) MSP430F233TPM ACTIVE LQFP Green (RoHS NIPDAU | CU NIPDAU Level-3-260C-168 HR -40 to 105 M430F233T &...
  • Page 82 PACKAGE OPTION ADDENDUM www.ti.com 16-Nov-2013 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples Drawing (4/5) MSP430F2471TRGCT ACTIVE VQFN Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 105 M430F2471T &...
  • Page 83 PACKAGE OPTION ADDENDUM www.ti.com 16-Nov-2013 Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples Drawing (4/5) MSP430F2491TRGCT ACTIVE VQFN Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 105 M430F2491T &...
  • Page 84 PACKAGE OPTION ADDENDUM www.ti.com 16-Nov-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
  • Page 85 PACKAGE MATERIALS INFORMATION www.ti.com 23-Jan-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Reel Reel Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1 (mm) MSP430F233TPMR LQFP 1000 330.0 24.4 13.0 13.0 16.0 24.0 MSP430F235TPMR...
  • Page 86 PACKAGE MATERIALS INFORMATION www.ti.com 23-Jan-2014 *All dimensions are nominal Device Package Type Package Drawing Pins Length (mm) Width (mm) Height (mm) MSP430F233TPMR LQFP 1000 336.6 336.6 41.3 MSP430F235TPMR LQFP 1000 336.6 336.6 41.3 MSP430F2410TPMR LQFP 1000 336.6 336.6 41.3 MSP430F2410TPMR LQFP 1000 367.0...
  • Page 90 MECHANICAL DATA MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996 PM (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,50 0,08 0,17 0,13 NOM 7,50 TYP Gage Plane 10,20 9,80 0,25 12,20 0,05 MIN 0 – 7 11,80 1,45 0,75 1,35 0,45 Seating Plane 1,60 MAX 0,08 4040152 / C 11/96...
  • Page 92 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue.

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