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BOOT SEQUENCE
Operation fl ow of normal start-up (Turning on the power without holding any switch)
Indication on the product
All the LEDs go out Voltage of 3.3 V is applied to the IC137 system reset (voltage
detector). Outputs about 10 us after detection.
Reset of the Flash ROM (IC133) is canceled.
Reset of the CPU (IC131) is canceled.
Starts fetching the program from address number 0 of the fl ash
ROM (IC133). Boot Program starts.
Starts accessing to the external SRAM (IC134).
Sets register of the SSP1SUB (IC132).
Initializes the external SDRAM (IC135) of the SSP1SUB
(IC132).
Resets the FPGA (IC123) and DICEII FLASH ROM (IC113).
Resets the MCI (IC111) and DICEII (IC103).
Cancels reset of the FPGA (IC123) and DICEII FLASH ROM
(IC113) in 10 (ms).
Cancels reset of the MCI (IC111) and DICEII (IC103) 10 (ms)
after the above procedure.
Hardware version is obtained from the register of the FPGA
(IC123).
Resets the panel micro computer (IC150).
Cancels reset of the panel micro computer (IC150) in 1 (us).
Checks the pressed switch and enters start-up mode.
Conducts check-sum inspection of the Main Program area.
In case of correct check-sum, operation of the Main Program is
started (From address 00020000h of the Flash ROM (IC133)).
In case of wrong check-sum, all the LEDs of the product fl ash
and no further processing is conducted.
Main Program starts.
Resets the panel micro computer (IC150).
Cancels reset of the panel micro computer (IC150) in 1 (us).
Opening screen
Shows the opening screen.
Conducts model identifi cation check.
If the result of the check is OK, the next procedure will be
conducted.
If the result of the check is disapproving, all the LEDs of the
product fl ash and no further processing is conducted.
Executes reset for the A/D converter (IC704, IC709, IC710 and
IC712) and D/A converter (IC751, IC809 and IC810).
Mutes all the channels of the Volume Controller (IC814).
Loads product setup data from the EEPROM (IC146).
Initializes the MCI (IC111). Starts communication with the
Normal Display
DICEII (IC103).
If the Word Clock is delivered from the DICEII (IC103) to SSP1
(IC131) correctly, the following processing will be conducted.
Changes the MUTE_OFF signal level from LOW to HIGH
to apply trigger for canceling mute to the muting circuit in
the FPGA. The following processing will be conducted if the
MUTE_REQ signal (IC131: EA06 (MUTE_REQ)) is turned to
HIGH level.
Executes reset of the A/D converter (IC704, IC709, IC710 and
IC712) and D/A converter (IC751, IC809 and IC810).
Sets the headphones level value in the product setup data to
the Volume Controller (IC814).
Cancels mute of the D/A converter (IC809, IC810).
Cancels mute of the SSP1 (IC131).
Function
Behavior of main signal lines
IC137: +3.3D
IC133: /RESET
IC131: ICN
IC131: CS0N(/CS0), MA*(MMA[*]), MD*(MMD[*]), RDN, WRN
IC131: CS2N(/CS2), MA*(MMA[*]), MD*(MMD[*]), RDN, WRN,
UBN, LBN
IC131: CS3N(/CS3), MA*(MMA[*]), MD*(MMD[*]), RDN, WRN,
UBN, LBN
IC132: CS2N(/CS), CS3N(/RAS), CS4N(/CAS), MA*(SMA[*]),
MD*(SMD[*]), RCLK, RDN, WRN, LBN
IC131: ED07(/RESET)
IC131: ED06(/RESETD)
IC131: ED07(/RESET)
IC131: ED06(/RESETD)
IC131: ED12(/CS60RD), MA*(MMA[*]), MD*(MMD[*])
IC131: ED05(/PN_IC)
IC131: ED05(/PN_IC)
IC131: ED05(/PN_IC)
IC131: ED05(/PN_IC)
IC131: ED01(/AD_RESET), ED02(/DAC_RESET, /DA_RESET)
IC131: ED14(/CS62WR), MA*(MMA[*]), MD*(MMD[*])
IC123: IO03(AVC_SCLK), IO04(AVC_DATAI), IO05(/AVC_CS)
IC131: ED08(/CS), ED09(SCK), ED10(SI)
IC131: CS4N(/CS4), MA*(MMA[*]), MD*(MMD[*])
IC131: ED11(/MUTE_OFF)
IC131: ED01(/AD_RESET), ED02(/DAC_RESET, /DA_RESET)
IC131: ED14(/CS62WR), MA*(MMA[*]), MD*(MMD[*])
IC123: IO03(AVC_SCLK), IO04(AVC_DATAI), IO05(/AVC_CS)
IC131: ED03
IC131: ED14(/CS62WR), MA*(MMA[*]), MD*(MMD[*])
IC123: IO26(/DA4358_CS), IO27(/DA4382_CS), IO28(DA_CDTI),
IO29(DA_CCLK)
MR816CSX/MR816X
65
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