Map - Syntacore SCR1 SDK Quick Start Manual

7. Appendix B. SDK Memory Map
Table 2. SCR1 SDK Memory Map
Base Length
Address
0x00000000 256 MB
0xF0000000 64 kB
0xF0040000 32 B
0xFF000000
0xFF000000 4 kB
0xFF001000 4 kB
0xFF010000 4 kB
0xFF020000 4 kB
0xFF021000 4 kB
0xFFFF0000 64 kB
14
Name Description
Reserved
Reserved for onboard DDR3L SDRAM.
TCM
SCR1 Tightly-Coupled Memory (refer to SCR1 EAS for
details).
Timer
SCR1 Timer registers (refer to SCR1 EAS for details).
MMIO BASE Base address for Memory-Mapped Peripheral IO
resources, resided externally to SCR1 core.
SYS_ID
32-bit System ID register.
BLD_ID
32-bit Build ID register.
UART
16550 UART registers (refer to Xilinx IP description for
details). Interrupt line is assigned to IRQ[0].
LED
LED PIO registers: PIO_LED_RGB and PIO_LED (offsets
0x0, 0x8).
BTN
Push
associated interrupt line assigned to IRQ[1].
SRAM
Onchip SRAM containing pre-programmed SCR Loader
firmware.
SCR1_CSR_MTVEC_BASE are both mapped here:
• SCR1_RST_VECTOR = 0xFFFFFF00
• SCR1_CSR_MTVEC_BASE = 0xFFFFFF80
Button PIO register:
SCR1_RST_VECTOR
PIO_PBUTTON. Has
and