Summary of Contents for Syntacore SCR1 SDK
- Page 1 SCR1 SDK. Digilent Arty Edition. Quick Start Guide Syntacore, info@syntacore.com Version 0.2, 2018-09-25...
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Page 2: Table Of Contents
Table of Contents Copyright notice ................ ... -
Page 3: Copyright Notice
Copyright notice Copyright by Syntacore LLC © 2017. ALL RIGHTS RESERVED. STRICTLY CONFIDENTIAL. Information contained in this material is confidential and proprietary to Syntacore LLC and its affiliates and may not be modified, copied, published, disclosed, distributed, displayed or exhibited, in either electronic or printed formats without written authorization of the Syntacore LLC. -
Page 4: Revision History
Revision history Version Date Description 2017-09-09 Initial revision. 2017-09-25 Updated for Vivado 2018.1 compatibility... -
Page 5: Introduction
Introduction This is a brief user guide allowing to get started with SCR1 SDK based on Arty FPGA Development Board from Digilent. It describes the board setup, procedure of software uploading and launching, and process of the FPGA’s content building and updating. -
Page 6: Required Hardware
1. Required Hardware Minimal set of hardware needed for SCR1 SDK, Arty Edition, includes just the following components: • Digilent’s Arty FPGA Development Board https://reference.digilentinc.com/reference/programmable-logic/arty/start • Standard USB Type A (m) - Type B micro (m) cable The minimal setup is shown in... -
Page 7: Sdk Setup
2. SDK Setup 2.1. Board’s USB connection Connect the USB Type A (m) - Type B micro (m) cable between Arty’s J10 (Shared USB JTAG/UART port) and your host computer. This connection performs three functions: • +5V Power Supply for Arty •... -
Page 8: Jtag Cable Adapter Connection
2.2. JTAG Cable Adapter connection SCR1 JTAG connection on the Arty board is shown in Figure 2. For pin-out of the JTAG port refer to Appendix A. JTAG Pin-Out("Table 1"). Figure 2. Arty Board with JTAG Cable Adapter Please, take into account that Olimex USB JTAG cable adapters after powering up (just after their USB cable connecting) hold debug connector’s SRSTn line in asserted state, actively holding entire processor subsystem in reset state. -
Page 9: Fpga Configuration Flash Programming
3. FPGA Configuration Flash Programming 3.1. Prerequisites For FLASH programming any of the following software tools is necessary: • Xilinx Vivado Design Suite 2018.1 • Xilinx Vivado Lab Edition 2018.1 • Xilinx Vivado WebPack Edition 2018.1 3.2. MCS-file MCS- and PRM-files are included into SDK repositories tree and could be obtained from here: <SDK_HOME>/images/arty/scr1/arty_scr1_mcs.7z Unpack this 7-Zip archive. -
Page 10: Getting Scr1 Running
3. Initiate FPGA re-configuration process (push PROG button) or SOC internal circuitry reset (push RESET button). 4. Terminal program should display SCR bootloader’s banner and prompt: SCR loader v1.0-scr1_RC Copyright (C) 2015-2017 Syntacore. All rights reserved. ISA: RV32IMC [40001104] IMPID: 17090700 SYSID: 17090400 BLDID: 17090701 Platform: arty_scr1, cpuclk 25MHz, sysclk 25MHz... - Page 11 1: xmodem load @addr g: start @addr d: dump mem m: modify mem i: platform info 2. Press button “1” 3. Enter required starting TCM address (in hex), and press “Enter”. Terminal starts to print “C” character periodically, indicating receiver’s requests to transmitter in accordance with XMODEM protocol.
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Page 12: Example: Dhrystone Run From Tcm Memory
+-----------[xmodem upload - Press CTRL-C to quit]---------------------+ |Sending dhry21-o3lto.bin, 107 blocks: Give your local XMODEM receive | |command now. |Bytes Sent: 13952 BPS:5468 |Transfer complete | READY: press any key to continue... +----------------------------------------------------------------------+ 8. When loading completes, status information will be shown: Xmodem successfully received 13952 bytes 4.3. -
Page 13: Fpga Image Modification
5. FPGA Image Modification 5.1. Prerequisites The following components are necessary: • Xilinx Vivado Design Suite 2018.1 5.2. FPGA Project Deployment 1. Install Arty’s board files Vivado directory structure, described here: https://reference.digilentinc.com/reference/software/vivado/board-files 2. Launch Vivado IDE, Console change current directory <FPGA_PROJECT_HOME_DIR>, where <FPGA_PROJECT_HOME_DIR>... -
Page 14: Configuration Flash Updating
After successful completion, the folder <FPGA_PROJECT_HOME_DIR>/arty_scr1/arty.runs/impl_1 should contain updated bit-file arty_scr1_top_new.bit and MCS-file arty_scr1_top_new.mcs for configuration FLASH chip programming. 5.5. Configuration FLASH Updating Refer to the section FPGA Configuration Flash Programming for details of that procedure. -
Page 15: Appendix A. Jtag Pin-Out
6. Appendix A. JTAG Pin-Out SCR1 JTAG port is routed to the onboard Pmod connector JD in accordance with "Table 1". Table 1. SCR1 JTAG Pin-Out JD bit PMod JD pin TRSTn SRSTn... -
Page 16: Map
7. Appendix B. SDK Memory Map Table 2. SCR1 SDK Memory Map Base Length Name Description Address 0x00000000 256 MB Reserved Reserved for onboard DDR3L SDRAM. 0xF0000000 64 kB SCR1 Tightly-Coupled Memory (refer to SCR1 EAS for details). 0xF0040000 32 B Timer SCR1 Timer registers (refer to SCR1 EAS for details). -
Page 17: Appendix C. Sdk Irqs
8. Appendix C. SDK IRQs Table 3. SCR1 IRQ Mapping IRQ line Device Notes UART Xilinx 16550 UART IP Xilinx PIO input register, connected to 4 onboard push-buttons. -
Page 18: Appendix D. Sdk Memory Mapped Registers
9. Appendix D. SDK Memory Mapped Registers 9.1. PIO_LED_RGB, Programmable IO LED RGB Control Register (0xFF020000) Table 4. Programmable IO LED RGB Control Register Bit(s) Name Description 0..2 LED0 LED[0] control: bits [2:0] correspond to {red, green, blue} partial LEDs of the onboard LD0. If a bit is 1, appropriate internal LED is illuminated. -
Page 19: Appendix E. Software Build Instructions
10. Appendix E. Software build instructions This build guide describes how to build software provided as a part of the SCR1 SDK. 10.1. SCR bootloader 10.1.1. Getting the sources $ git clone git@github.com:syntacore/sc-bl.git 10.1.2. Building SCR bootloader Follow the instructions in sc-bl/README.md to build bootloader for target plaforms ('scbl.hex' for Terasic DE10-Lite, 'scbl.mem' for Digilent Arty).
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