Fpga Image Modification; Prerequisites; Fpga Project Deployment; Building Bitstream File - Syntacore SCR1 SDK Quick Start Manual

5. FPGA Image Modification

5.1. Prerequisites

The following components are necessary:
• Xilinx Vivado Design Suite 2018.1

5.2. FPGA Project Deployment

1. Install Arty's board
https://reference.digilentinc.com/reference/software/vivado/board-files
2. Launch Vivado
<FPGA_PROJECT_HOME_DIR>, where
<FPGA_PROJECT_HOME_DIR> = <SDK_HOME>/fpga/arty/scr1
3. In Tcl Console, execute the following command
source ./arty_scr1.tcl
The script "arty_scr1.tcl" creates Vivado project arty_scr1 and prepares used IPs for further
synthesis.

5.3. Building Bitstream File

In the just deployed and open project, click on
• Project Navigator / Program and Debug / Generate Bitstream button
and press OK on the following Vivado confirmation request. This will start the process of full design
rebuilding, from synthesis through bitstream file generation.

5.4. Onchip Memory Update

Due to Vivado Design Suite specifics described in the Xilinx AR #63042, initialization of the onchip
memories is performed after bitstream file generation, by a standalone script mem_update.tcl.
In the Tcl Console, execute the following commands:
cd <FPGA_PROJECT_HOME_DIR>/arty_scr1
source "../../../scripts/xilinx/mem_update.tcl"
files in Vivado
IDE, and in its
directory structure,
Tcl Console change
as described
current directory
here:
to the
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