Denon DRA-100 Service Manual page 72

Pin Name
115 C67GND
116 C67P3V3
117 CH6_FB1
118 CH6_FB0
119 CH6_REF2
120 CH6_REF1
121 C6GND
122 C6P3V3
123 CH6_REF0
124 C6P1V8
125 GND
126 P1V8
127 CKO1P3V3
128 PWMCK1_OUT
129 CKO1GND
130 CKO1P1V8
131 MCK1_OUT_BAR
132 MCK1_OUT
133 C5P1V8
134 CH5_REF0
135 C5P3V3
136 C5GND
137 CH5_REF1
Pin Name
Production Information
© 2012 Cambridge Silicon Radio Limited
This material is subject to CSR's non-disclosure agreement.
138 CH5_REF2
139 CH5_FB0
140 CH5_FB1
141 C45P1V8
142 C45GND
143 C45P3V3
144 CH4_FB1
145 CH4_FB0
146 CH4_REF2
147 CH4_REF1
148 C4GND
149 C4P3V3
150 CH4_REF0
151 C4P1V8
152 CKIP1V8
153 CKIGND1
154 MCK_IN
155 CKIP3V3
156 MCK_IN_BAR
157 CKIGND2
158 C3P1V8
159 CH3_REF0
160 C3P3V3
Production Information
© 2012 Cambridge Silicon Radio Limited
This material is subject to CSR's non-disclosure agreement.
Function Description
- Ground
- 3.3 V I/O supply (quiet)
Bidirectional, pull-up Channel 6 high resolution feedback input
or channel 6/7 I²S output bit clock
Bidirectional, pull-up Channel 6 low resolution feedback input
Output, tristate Channel 6 reference 2 output
Output, tristate Channel 6 reference 1 output
- Ground
- 3.3 V I/O supply (quiet)
Output, tristate Channel 6 reference 0 output
- 1.8 V core supply (quiet)
- Ground
- 1.8 V core supply
- 3.3 V I/O supply (quiet)
Output, tristate PWM triangle generator output channels
4, 5, 6, 7
- Ground
- 1.8 V core supply (quiet)
Output, tristate 108 MHz Master clock bar output
channels 4, 5, 6, 7
Output, tristate 108 MHz Master clock output channels 4,
5, 6, 7
- 1.8 V core supply (quiet)
Output, tristate Channel 5 reference 0 output
- 3.3 V I/O supply (quiet)
- Ground
Output, tristate Channel 5 reference 1 output
Function Description
Output, tristate Channel 5 reference 2 output
Bidirectional, pull-up Channel 5 low resolution feedback input
or channel 4/5 I²S output word clock
Bidirectional, pull-up Channel 5 high resolution feedback input
or channel 4/5 I²S output data
- 1.8 V core supply (quiet)
- Ground
- 3.3 V I/O supply (quiet)
Bidirectional, pull-up Channel 4 high resolution feedback input
or channel 4/5 I²S output bit clock
Bidirectional, pull-up Channel 4 low resolution feedback input
Output, tristate Channel 4 reference 2 output
Output, tristate Channel 4 reference 1 output
- Ground
- 3.3 V I/O supply (quiet)
Output, tristate Channel 4 reference 0 output
- 1.8 V core supply (quiet)
- 1.8 V core supply (quiet)
- Ground
Input/output 108 MHz Master clock input
- 3.3 V I/O supply (quiet)
Input/output 108 MHz Master clock bar input or Master
clock output
- Ground
- 1.8 V core supply (quiet)
Output, tristate Channel 3 reference 0 output
- 3.3 V I/O supply (quiet)
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CS-225959-DSP6
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