Msc Cpu And Cpu Interface - Cisco CRS-1 System Description

Chapter 5 Line Cards, Physical Layer Interface Modules, and Shared Port Adapters Overview
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MSC CPU and CPU Interface

As shown in
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The CPU subsystem includes:
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The CPU interface provides the interface between the CPU subsystem and the other ASICs on the MSC
and PLIM.
The MSC also contains a service processor (SP) module that provides:
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The SP, CPU subsystem, and CPU interface work together to perform housekeeping, communication,
and control plane functions for the MSC. The SP controls card power up, environmental monitoring, and
Ethernet communication with the line card chassis RPs. The CPU subsystem performs a number of
control plane functions, including FIB download receive, local PLU and TLU management, statistics
gathering and performance monitoring, and MSC ASIC management and fault-handling. The CPU
interface drives high-speed communication ports to all ASICs on the MSC and PLIM. The CPU talks to
the CPU interface through a high-speed bus attached to its memory controller.
OL-10805-10
Back-pressure signalling for the queues
Dynamically shared buffer memory for each queue
A loopback function where transmitted data can be looped back to the receive side
Figure 5-2, the MSC contains a central processing unit (CPU) that performs these functions:
MSC configuration
Management
Protocol control
A CPU chip
A Layer 3 cache
NVRAM
A flash boot PROM
A memory controller
Memory, a dual in-line memory module (DIMM) socket, providing up to 2 GB of 133 MHz DDR
SDRAM on the CRS-MSC, up to 2 GB of 166 MHz DDR SDRAM on the CRS-MSC-B, and up to
8GB of 533MHz DDR2 SDRAM on the CRS-MSC-140G.
MSC and PLIM power-up sequencing
Reset sequencing
JTAG configuration
Power monitoring
Cisco CRS Carrier Routing System 4-Slot Line Card Chassis System Description
Line Cards and PLIMs Overview
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