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Chapter 4 System Support
4.4.4
INTERRUPTS
The microprocessor uses two types of interrupts; maskable and nonmaskable. A maskable
interrupt can be enabled or disabled within the microprocessor by the use of the STI and CLI
instructions. A nonmaskable interrupt cannot be masked off within the microprocessor but may
be inhibited by hardware or software means external to the microprocessor.
4.4.4.1 Maskable Interrupts
The maskable interrupt is a hardware-generated signal used by peripheral functions within the
system to get the attention of the microprocessor. Peripheral functions produce a unique INTA-D
(PCI) or IRQ0-15 (ISA) signal that is routed to interrupt processing logic that asserts the
interrupt (INTR) input to the microprocessor. The microprocessor halts execution to determine
the source of the interrupt and then services the peripheral as appropriate.
IRQ1,3..7,
9..12,
14,15
ISA Peripherals
& SM Functions
PIRQA-..D-
PCI Peripherals
Figure 4–8. Maskable Interrupt Processing, Block Diagram
The South Bridge component, which includes the equivalent of two 8259 interrupt controllers
cascaded together, handles the standard AT-type (ISA) interrupt signals (IRQn). The South
Bridge also receives the PCI interrupt signals (PIRQA-..PIRQD-) from PCI devices. The PCI
interrupts can be configured by PCI Configuration Registers 55h..57h to share the standard ISA
interrupts (IRQn). The power-up default configuration has the PIRQn disabled. Table 4-13 lists
the standard source configuration for maskable interrupts and their priorities. If more than one
interrupt is pending, the highest priority (lowest number) is processed first.
4-20
Compaq Deskpro 4000 and 6000 Personal Computers
featuring the Pentium II Processor
South Bridge Component
IRQ9..12,
14,15
Interrupt
Cntlr. 2
PCI IRQ
Routing
First Edition - October 1997
IRQ1,3..7
Interrupt
Cntlr. 1
IRQ2
INTR
Microprocessor
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