Texas Instruments ADS869 Series Manual

Texas Instruments ADS869 Series Manual

18-bit, 500-ksps, 4- and 8-channel, single-supply, sar adcs with bipolar input ranges

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ADS869x 18-Bit, 500-kSPS, 4- and 8-Channel, Single-Supply, SAR ADCs with
1 Features
18-Bit ADCs with Integrated Analog Front-End
1
4-, 8-Channel MUX with Auto and Manual Scan
Channel-Independent Programmable Inputs:
– ±10.24 V, ±5.12 V, ±2.56 V
– 10.24 V, 5.12 V
5-V Analog Supply: 1.65-V to 5-V I/O Supply
Constant Resistive Input Impedance: 1 MΩ
Input Overvoltage Protection: Up to ±20 V
On-Chip, 4.096-V Reference with Low Drift
Excellent Performance:
– 500-kSPS Aggregate Throughput
– DNL: ±0.5 LSB; INL: ±1.5 LSB
– Low Drift for Gain Error and Offset
– SNR: 93.5 dB; THD: –105 dB
– Low Power: 65 mW
AUX Input → Direct Connection to ADC Inputs
ALARM → High and Low Thresholds per Channel
SPI™-Compatible Interface with Daisy-Chain
Industrial Temperature Range: –40°C to 125°C
TSSOP-38 Package (9.7 mm × 4.4 mm)
Block Diagram
AVDD
1 M:
AIN_0P
OVP
2nd-Order
PGA
AIN_0GND
LPF
OVP
1 M:
V
B0
1 M:
AIN_1P
OVP
2nd-Order
PGA
AIN_1GND
LPF
OVP
1 M:
V
B1
1 M:
AIN_2P
OVP
2nd-Order
PGA
AIN_2GND
LPF
OVP
1 M:
V
B2
1 M:
AIN_3P
OVP
2nd-Order
PGA
AIN_3GND
LPF
OVP
1 M:
V
B3
1 M:
AIN_4P
OVP
2nd-Order
PGA
AIN_4GND
LPF
OVP
1 M:
V
B4
1 M:
AIN_5P
OVP
2nd-Order
PGA
AIN_5GND
LPF
OVP
1 M:
V
B5
1 M:
AIN_6P
OVP
2nd-Order
PGA
AIN_6GND
LPF
OVP
1 M:
V
B6
1 M:
AIN_7P
OVP
2nd-Order
PGA
AIN_7GND
LPF
OVP
1 M:
V
B7
AUX_IN
Internal ADC Operating as 16-Bit ADC
AUX_GND
AGND
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
Sample &
Product
Buy
Folder
Bipolar Input Ranges
DVDD
ADS8698
ADC
ADS8694
Driver
ADC
Driver
Digital
ADC
Logic
Driver
and
CS
Interface
SCLK
ADC
Driver
SDI
SDO
18-Bit
ADC
Driver
SAR ADC
DAISY
REFSEL
ADC
Oscillator
Driver
RST / PD
ALARM
ADC
REFCAP
Driver
REFIO
ADC
Driver
4.096-V
Reference
DGND
REFGND
Tools &
Technical
Software
Documents
2 Applications
Power Automation
Protection Relays
PLC Analog Input Modules
3 Description
The ADS8694 and ADS8698 are 4- and 8-channel,
integrated data acquisition systems based on a 18-bit
successive approximation (SAR) analog-to-digital
converter (ADC), operating at a throughput of
500 kSPS. The devices feature integrated analog
front-end circuitry for each input channel with
overvoltage protection up to ±20 V, a 4- or 8-channel
multiplexer with automatic and manual scanning
modes, and an on-chip, 4.096-V reference with low
temperature drift. Operating on a single 5-V analog
supply, each input channel on the devices can
support true bipolar input ranges of ±10.24 V,
±5.12 V, and ±2.56 V, as well as unipolar input
ranges of 0 V to 10.24 V and 0 V to 5.12 V. The gain
of the analog front-end for all input ranges is
accurately trimmed to ensure a high dc precision. The
input range selection is software-programmable and
independent for each channel. The devices offer a
1-MΩ constant resistive input impedance irrespective
of the selected input range.
The ADS8694 and ADS8698 offer a simple SPI-
compatible serial interface to the digital host and also
support daisy-chaining of multiple devices. The digital
supply operates from 1.65 V to 5.25 V, enabling
direct interface to a wide range of host controllers.
Device Information
PART NUMBER
ADS869x
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Gain Error versus Temperature
0.05
0.03
0.01
-0.01
-0.03
-0.05
±40
±7
Support &
Reference
Community
Design
ADS8694, ADS8698
SBAS686 – JULY 2015
(1)
PACKAGE
BODY SIZE (NOM)
TSSOP (38)
9.70 mm × 4.40 mm
----- ± 2.5*V
REF
----- ] 1.25*V
REF
----- ] 0.625*V
----- + 2.5*V
REF
-----+1.25*V
REF
26
59
92
o
Free-Air temperature (
C)
REF
125
C027

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  • Page 1 Sample & Support & Reference Product Tools & Technical Community Design Folder Software Documents ADS8694, ADS8698 SBAS686 – JULY 2015 ADS869x 18-Bit, 500-kSPS, 4- and 8-Channel, Single-Supply, SAR ADCs with Bipolar Input Ranges 1 Features 2 Applications • 18-Bit ADCs with Integrated Analog Front-End •...
  • Page 2: Table Of Contents

    8.1 Overview ..............13 Mechanical, Packaging, and Orderable 8.2 Functional Block Diagram ........Information ............8.3 Feature Description..........4 Revision History DATE REVISION NOTES July 2014 Initial release. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 3: Pin Configuration And Functions

    Analog input Auxiliary input channel: positive input. Decouple with AUX_GND on pin 11. AUX_GND Analog input Auxiliary input channel: negative input. Decouple with AUX_IN on pin 10. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 4 Active high alarm output Digital output Data output for serial communication SCLK Digital input Clock input for serial communication Digital input Active low logic input; chip-select signal Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 5: Specifications

    °C/W Junction-to-case (bottom) thermal resistance °C/W θJC(bot) (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 6: Electrical Characteristics

    (C) Typical value only for information, provided by design simulation. (2) Ideal input span, does not include gain or offset error. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 7 (3) LSB = least significant bit. (4) This parameter is the endpoint INL, not best-fit INL. (5) FSR = full-scale range. (6) Does not include the shift in offset over time. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 8 (9) Memory crosstalk is measured by applying a full-scale sinusoidal signal up to 10 kHz to a channel that is selected in the multiplexing sequence, and measuring its effect on the output of the next selected channel for all combinations of input channels. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 9 Only for SDO µA Internal pin capacitance TEMPERATURE RANGE Operating free-air temperature –40 °C (10) Does not include the variation in voltage resulting from solder-shift and long-term effects. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 10: Timing Requirements: Serial Interface

    PH_CS SCLK D_CKCS SU_CSCK PH_CK PL_CK SCLK HT_CKDO DZ_CSDO DV_CSDO SU_DOCK Data from sample N SU_DICK HT_CKDI SU_DSYCK HT_CKDSY DAISY Figure 1. Serial Interface Timing Diagram Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 11: Typical Characteristics

    = ±2.5 × V range = ±1.25 × V Figure 6. DC Histogram for Mid-Scale Inputs (±2.5 × V Figure 7. DC Histogram for Mid-Scale Inputs (±1.25 × V Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 12 Codes (LSB) Free-Air Temperature ( C014 C013 Range = ±2.5 × V All input ranges Figure 13. Typical INL for All Codes Figure 12. DNL vs Temperature Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 13 Range = ±1.25 × V Range = ±2.5 × V Figure 19. INL vs Temperature (±1.25 × V Figure 18. INL vs Temperature (±2.5 × V Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 14 C025 Range = ±2.5 × V Range = ±2.5 × V Figure 24. Typical Histogram for Offset Drift Figure 25. Offset Error vs Temperature Across Channels Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 15 SINAD = 92.2dB, THD = 107 dB, SFDR = 110 dB Figure 30. Typical FFT Plot (±2.5 × V Figure 31. Typical FFT Plot (±1.25 × V Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 16 1000 10000 ±40 ±7 Free-Air Temperature ( Input Frequency (Hz) C038 C037 = 1 kHz Figure 36. SNR vs Temperature Figure 37. SINAD vs Input Frequency Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 17 Input Frequency (Hz) C044 C043 Input = 2 × maximum input voltage Figure 42. Isolation Crosstalk vs Frequency Figure 43. Memory Crosstalk vs Frequency for Overrange Inputs Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 18 ±7 Free-Air Temperature( Free-Air Temperature ( C063 C060 Figure 48. AVDD Current vs Temperature for the ADS8694 Figure 49. AVDD Current vs Temperature (During Sampling) (STANDBY) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 19 = 4.096 V, and f = 500 kSPS, unless otherwise noted. SAMPLE ±40 ±7 Free-Air Temperature ( C077 Figure 50. AVDD Current vs Temperature (Power Down) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 20: Detailed Description

    Driver AIN_6GND REFCAP 1 M: REFIO 1 M: AIN_7P 2nd-Order AIN_7GND Driver 4.096-V 1 M: Reference AUX_IN Internal ADC operating as 16-bit AUX_GND AGND DGND REFGND Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 21: Feature Description

    In order to maintain the dc accuracy of the system, matching the external source impedance on the AIN_nP input pin with an equivalent resistance on the AIN_nGND pin is recommended. This matching helps to cancel any additional offset error contributed by the external resistance. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 22 OVP voltage range. Note that higher source impedance results in gain errors and contributes to overall system noise performance. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 23 C004 Figure 53. I-V Curve for an Input OVP Circuit Figure 54. I-V Curve for an Input OVP Circuit (AVDD = 5 V) (AVDD = Floating) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 24 18-bit accuracy within the acquisition time of the ADC, irrespective of the input levels on the respective channels. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 25 The internal or external reference selection is determined by an external REFSEL pin. The devices have a built-in buffer amplifier to drive the actual reference input of the internal ADC core for maximizing performance. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 26 3300 production devices. -0.6 -0.2 Error in REFIO Voltage (mV) C064 Figure 58. Internal Reference Accuracy at Room Temperature Histogram Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 27 AVDD = 5 V, number of devices = 30, ΔT = –40°C to 125°C Figure 60. Variation of the Internal Reference Output Figure 61. Internal Reference Temperature Drift Histogram (REFIO) Across Supply and Temperature Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 28 REFCAP pin as possible for decoupling high-frequency signals. Do not use the internal buffer to drive external ac or dc loads because of the limited current output capability of this buffer. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 29 AUX channel. Some key requirements of the driving amplifier are discussed in the Input Driver for the AUX Channel section. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 30 SFDR = 102 dB, number of points = 64k Figure 67. Typical FFT Plot Figure 68. SNR, SINAD, and THD vs Temperature (AUX Channel) (AUX Channel) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 31 • is the noise gain of the front-end circuit, which is equal to 1 in a buffer configuration. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 32 2.56 V –2.56 V 5.12 V 19.53125 0 to 2.5 × V 10.24 V 10.24 V 39.0625 0 to 1.25 × V 5.12 V 5.12 V 19.53125 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 33 Hysteresis Channel n Active Alarm Flag Channel n ADC Output Tripped Alarm Flag Channel n Channel n SCLK Alarm Flag Read Figure 72. Alarm Functionality Schematic Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 34: Device Functional Modes

    The SDO line goes low after the entire data frame is output and goes to a Hi-Z state when CS goes high. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 35 When the RST/PD pin is pulled back to a logic high level, the devices wake-up in a default state in which the program registers are reset to their default values. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 36 73. However, there are applications that require multiple ADCs but the host controller has limited interfacing capability. This section describes two connection topologies that can be used to address the requirements of such applications. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 37 70 SCLK cycles for the entire data frame. Note that the overall throughput of the system is proportionally reduced with the number of devices connected in a daisy-chain configuration. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 38 (SDO and SCLK). This loading can lead to digital timing errors. This limitation can be overcome by using digital buffers on the shared outputs from the host controller before being fed into additional devices. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 39 (PROG mode), then the device retains the current settings of the program registers. The device goes back to IDLE mode and waits for the user to enter a proper command to execute the program register read or write configuration. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 40 SDI is Low in a Data Frame STDBY Command ± 8200h Data from Sample N Figure 80. Enter and Remain in STDBY Mode Timing Diagram Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 41 STDBY Mode on CS Rising Edge Min width of CS HIGH = 20µs for valid sample SCLK AUTO_RST Command MAN_CH_n Command Figure 81. Exit STDBY Mode Timing Diagram Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 42 Device exits PWR_DN Mode, but frame after recovery from waits 15ms for 16-bit settling PWR_DN mode SCLK AUTO_RST Command MAN_CH_n Command Invalid Data Figure 83. Exit PWR_DN Mode Timing Diagram Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 43 Mode Setting AUTO_RST Mode AUTO_RST Mode (Channel sequence restarted from (Channels 0-2 are selected in sequence.) lowest count.) Figure 85. Device Operation Example in AUTO_RST Mode Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 44 (Ch 1 is selected and device continuously converts Ch 1 if NO_OP command is provided) (Transition from Ch1 to Ch 3) Figure 87. Device Operation in MAN_Ch_n Mode Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 45 Based on Previous Mode Setting MAN_Ch_n Mode AUTO_RST Mode Figure 89. Transitioning from MAN_Ch_n to AUTO_RST Mode (Channels 0 and 5 are Selected for Auto Sequence) Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 46 CS Rising Edge command or after reading frame data. SCLK Reset Program Registers (RST) ± 8500h Data from Sample N Figure 90. Reset Program Registers (RST) Timing Diagram Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 47: Register Maps

    Manual AUX Selection 0000 0000 E000h AUX channel input is selected (MAN_AUX) (1) Shading indicates bits or registers not included in the 4-channel version of the device. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 48 ADDR[6:0] DIN[7:0] Sample SCLK ADDR [6:0] DIN [7:0] X X X X Data written into register, DIN [7:0] Figure 91. Program Register Write Cycle Timing Diagram Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 49 (Bits 7-0) ADDR[6:0] XXXXX 0000 000 DOUT[7:0] SCLK ADDR [6:0] X X X X X X DOUT [7:0] Figure 92. Program Register Read Cycle Timing Diagram Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 50 (2) Shading indicates bits or registers that are not included in the 4-channel version of the device. A write operation on any of these bits or registers has no effect on device behavior. A read operation on any of these bits or registers outputs all 1's on the SDO line. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 51 Ch 7 High Threshold LSB CH7_HT[7:0] Ch 7 Low Threshold MSB CH7_LT[15:8] Ch 7 Low Threshold LSB CH7_LT[7:0] COMMAND READ BACK (Read-Only) Command Read Back COMMAND_WORD[7:0] Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 52 Channel 0 enable. 0 = Channel 0 is not selected for sequencing in AUTO_RST mode 1 = Channel 0 is selected for sequencing in AUTO_RST mode Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 53 AUTO_RST sequence 1 = The analog front end on channel 0 is powered down and channel 0 cannot be included in the AUTO_RST sequence Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 54 0111 = Channel 7 (valid only for the ADS8698) Two bits of device address (mainly useful in daisy-chain mode). Three LSB bits of input voltage range (see the Range Select Registers section). Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 55 0010 = Input range is set to ±0.625 x V 0101 = Input range is set to 0 to 2.5 x V 0110 = Input range is set to 0 to 1.25 x V Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 56 0 = No alarm detected Tripped Alarm Flag Ch4 1 = Alarm detected Tripped Alarm Flag Ch3 Tripped Alarm Flag Ch2 Tripped Alarm Flag Ch1 Tripped Alarm Flag Ch0 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 57 Each individual bit indicates an active high or low alarm flag status for each channel, as per the alarm flags register for channels 0 to 7. 0 = No alarm detected 1 = Alarm detected Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 58 Each individual bit indicates an active high or low alarm flag status for each channel, as per the alarm flags register for channels 0 to 7. 0 = No alarm detected 1 = Alarm detected Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 59 Ch 7 Low Threshold MSB CH7_LT[15:8] Ch 7 Low Threshold LSB CH7_LT[7:0] (1) Shading indicates bits or registers not included in the 4-channel version of the device. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 60 0000 0001 = MSB byte is 01h 0000 0010 to 1110 1111 = MSB byte is 02h to FEh 1111 1111 = MSB byte is FFh Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 61 0000 0001 = MSB byte is 01h 0000 0010 to 1110 1111 = MSB byte is 02h to FEh 1111 1111 = MSB byte is FFh Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 62 LEGEND: R = Read only; -n = value after reset Table 26. Command Read-Back Register Field Descriptions Field Type Reset Description COMMAND_WORD[15:8] Command executed in previous data frame. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 63: Application And Implementation

    The key electrical parameters include amplitude, frequency, and phase, which are important for calculating the power factor, power quality, and other parameters of the power system. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 64 For a step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test results, see Phase Compensated 8-Channel, Multiplexed Data Acquisition System for Power Automation Reference Design (TIDU427). Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 65 C lines for the TCA6408A. The TCA6408A controls the low R opto-switch (TLP3123) that is used to switch between voltage-to-current input modes. The input channel configuration is done in microcontroller firmware. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 66: Power-Supply Recommendations

    Input Frequency (Hz) C046 C045 Code output near 131072 Code output near 131072 Figure 110. PSRR Without a Decoupling Capacitor Figure 111. PSRR With a Decoupling Capacitor Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 67: Layout

    COG (NPO) ceramic capacitors provide the best capacitance precision. The type of dielectric used in COG (NPO) ceramic capacitors provides the most stable electrical properties over voltage, frequency, and temperature changes. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 68: Layout Example

    16: AIN_0P 23: AIN_3P 17: AIN_0GND 22: AIN_3GND 18: AIN_1P 21: AIN_2P 19: AIN_1GND 20: AIN_2GND Analog Pins Figure 112. Board Layout for the ADS8694 and ADS8698 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 69: Device And Documentation Support

    All other trademarks are the property of their respective owners. 12.5 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
  • Page 70: Mechanical, Packaging, And Orderable Information

    This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: ADS8694 ADS8698...
  • Page 71 PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples Drawing (4/5) ADS8694IDBT ACTIVE TSSOP Green (RoHS NIPDAU Level-2-260C-1 YEAR -40 to 125 ADS8694 &...
  • Page 72 PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
  • Page 73 PACKAGE MATERIALS INFORMATION www.ti.com 21-Jul-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Reel Reel Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1 (mm) ADS8694IDBTR TSSOP 2000 330.0 16.4 10.2 12.0 16.0 ADS8698IDBTR TSSOP...
  • Page 74 PACKAGE MATERIALS INFORMATION www.ti.com 21-Jul-2015 *All dimensions are nominal Device Package Type Package Drawing Pins Length (mm) Width (mm) Height (mm) ADS8694IDBTR TSSOP 2000 367.0 367.0 38.0 ADS8698IDBTR TSSOP 2000 367.0 367.0 38.0 Pack Materials-Page 2...
  • Page 75: Notes

    PACKAGE OUTLINE DBT0038A TSSOP - 1.2 mm max height SCALE 2.000 SMALL OUTLINE PACKAGE SEATING 6.55 6.25 TYP PLANE 0.1 C PIN 1 INDEX AREA 38 X 0.5 9.75 9.65 NOTE 3 38 X 0.23 0.17 4.45 1.2 MAX C A B 4.35 NOTE 4 0.25...
  • Page 76 EXAMPLE BOARD LAYOUT DBT0038A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 38 X (1.5) SYMM (R0.05) TYP 38 X (0.3) 38 X (0.5) SYMM (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK METAL UNDER SOLDER MASK METAL OPENING SOLDER MASK...
  • Page 77 EXAMPLE STENCIL DESIGN DBT0038A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 38 X (1.5) SYMM (R0.05) TYP 38 X (0.3) 38 X (0.5) SYMM (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220221/A 05/2020 NOTES: (continued) 8.
  • Page 78 TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2020, Texas Instruments Incorporated...

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