Digital Interface - Texas Instruments ADS8472EVM User Manual

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The reference voltage provides the scale factor for the conversion result. The input voltage is measured
against the reference voltage. It is imperative the reference voltage be clean, low noise and well
decoupled.
The default configuration is to use the internal on-chip reference.
4

Digital Interface

The ADS8472EVM is designed for easy interfacing to multiple platforms. The digital interface input and
output signals of the converter are on connectors P2, P3, J6 and J7. These are 0.1" on-centers, plug and
socket connectors, allowing the user to plug the ADS8472EVM onto the various motherboard interface
cards from Texas Instruments, or ribbon cable onto the user development board. The following tables list
the connector pin outs.
Description
Not connected
Reserved
Reserved
Address line 0
Address line 1
Address line 2
Reserved
Reserved
Convert Start
Interrupt pin
Conversions are initiated on the falling edge of the convert start signal. It is therefore critical when
measuring large amplitude and/or high frequency input signals, the user provide a clean low jitter convert
start pulse.
The convert start signal can be applied to the ADS8472 from the decoder outputs or from connector P3
pin 17. Address decoder SN74ACH138 is used to generate the read (RD) and conversion start (CONVST)
signals to the converter. Jumpers W3 and W4 allow the user to assign these two signals to different
addresses in memory. This allows for the stacking of up to two ADS8472EVMs into processor memory.
See Table 3 for jumper settings. If the user applies a convert start signal directly on P3 pin 17, then be
sure to short W6 pins 1-2. This will bypass the decoder output selected by position of W4.
Note, the evaluation module does not allow chip select (CS) line of the converter to be assigned to
different memory locations. It is therefore suggested the CS line be grounded or wired to an appropriate
signal of the processor.
Reference
Designator
W1 Set digital buffer supply voltage to +5V
Set digital buffer supply voltage to +3.3V
W2 Apply inverted BUSY to INTC signal
Apply BUSY signal to INTC signal
W3 Set RD signal to add[0x3]
Set RD signal to add[0x4]
W4 Set CONVST signal to add[0x1]
Set CONVST signal to add[0x2]
(1)
† Indicates factory installed option.
SLAU203 – February 2007
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Table 3. Pinout for Parallel Control Connector P3
Signal Name Connector.Pin#
DC_CS P3.1
N/A P3.3
N/A P3.5
A0 P3.7
A1 P3.9
A2 P3.11
N/A P3.13
N/A P3.15
DC_CONVST P3.17
INTC P3.19
Table 4. Jumper Settings
Description
Signal Name
P3.2 +
P3.4 GND
P3.6 GND
P3.8 GND
P3.10 GND
P3.12 GND
P3.14 GND
P3.16 GND
P3.18 GND
P3.20 GND
1-2
Installed
Not installed
Installed †
Not installed
Installed
Not installed
Installed
Not installed
Digital Interface
Description
Non-inverting Input Channel
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
Ground
2-3
Not installed
(1)
Installed †
(1)
Not installed
Installed
Not installed
Installed
Not installed
Installed
ADS8472EVM 5