Hisense RL-32B02 Quick Start Manual page 22

video/audio encoding data stream mixing. It can minimize the dimensions, cost and power
consumption of MPEG-II application system.
The whole module is mainly composed of nine parts, namely, clock generator circuit (PLL), Audio
Encoder, Video Encoder, Multiplexer, Controller, TBC Controller, Host/SDRAM Interface
Controller, Serial Interface Controller and Boot Rom.
Audio and video encoders: to encode the converted A/D data stream.
Multiplexer: to mix the data produced by audio and video encoders in accordance with the specified
mode in order to output the 8-digit compressed data from the output port of potential flow.
Controller: It is the core CPU of the whole encoding chip and a 32Bit RISC processor. It carries out
the image compression task through a preset Firmware.
TBC Controller: to store the externally-input video data and send them to the video encoder.
TBC (Time Base Corrector): to realize its function by making use of the data cached in SDRAM
video encoder.
Host/SDRAM Interface Controller: It arbitrates the access requests on the internal register of
SDRAM or MB86391 from the external host or the internal modules of MB86391 and can also be
used as the command interface between the encoder and the host.
Serial Interface Controller: It is used as the interface for firmware downloading to SDRAM in the
serial boot and can also be used as the command interface between the encoder and the host.
Boot Rom: It stores the boot program of the internal controller.
MB86391 Internal Structural Diagram
22