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ISL5217EVAL1
JUMPER
JP1
JP2
JP3
JP4 (Note)
JP5 (Note)
JP6 (Note)
JP7
JP8
JP9
JP10
JP11
JP12
JP13
J9-13 to J9-14
NOTE: Jumpers 4-6 have other possible combinations, as detailed on the schematic for Master/Slave configurations of multiple evaluation CCAs.
AN9910 Rev.1.00
June 2001
TABLE 1. JUMPER CONFIGURATION
TYPE
POSITION
On/Off
On
Off
On/Off
On
Off
3-Point
Off
1-2
2-3
3-Point
Off
1-2
2-3
3-Point
Off
1-2
2-3
3-Point
Off
1-2
2-3
3-Point
Off
1-2
2-3
3-Point
Off
1-2
2-3
3-Point
Off
1-2
2-3
3-Point
Off
1-2
2-3
3-Point
Off
1-2
2-3
3-Point
Off
1-2
2-3
3-Point
Off
1-2
2-3
On/Off
On
Of
DEFAULT
Off
Enables SYNCO as the CAS-SYNC0 J3-39 Output.
Disables SYNCO as the CAS-SYNC0 J3-39 Output.
Off
Enables UPDA as the CAS-SYNC0 J3-39 Output.
Disables UPDA as the CAS-SYNC0 J3-39 Output.
2-3
Disables the 217-CLK Input
Enables BIT-CLK as the 217-CLK Input
Enables CLK2 as the 217-CLK Input
2-3
Disables the BIT-CLK Input
Enables the input of BIT-CLK from the CAS-OUT-CLK J3-19.
Enables the output of CLK3 to the CAS-OUT-CLK J3-19.
2-3
Disables the BIT-CLK Input
INVALID
Enables the U6 or J11 CLK Input.
2-3
Disables the CAS-IN-CLK Input
Enables the 50 termination through R13.
Enables the output of CLK3 as the CAS-IN-CLK J1-19.
2-3
25-50MHz Frequency Range Select for prog. clk
15-30 MHz Frequency Range Select for prog. clk
40-110 MHz Frequency Range Select for prog. clk
Off
Selects Normal Mode for CPLD-PROG
Selects Program Mode for CPLD-PROG
Selects Normal Mode for CPLD-PROG
1-2
Disables the DAC-CLK Input Signal
Enables CLK as the DAC-CLK Input signal
Enables ISTRB as the DAC-CLK Input Signal
Off
Select "0" for BADDR3
Select "0" for BADDR3
Select "1" for BADDR3
Off
Select "0" for BADDR2
Select "0" for BADDR2
Select "1" for BADDR2
Off
Select "0" for BADDR1
Select "0" for BADDR1
Select "1" for BADDR1
Off
Select "0" for BADDR0
Select "0" for BADDR0
Select "1" for BADDR0
On
Selects TDO-CPLD for TDO.
TDO Not Routed on Board.
FUNCTION
Page 5 of 6
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