Renesas QB-RL78D1A2 User Manual page 33

QB-RL78D1A2 In-Circuit Emulator
- The detection voltage value of the voltage detector (LVD)
LVD detection voltage differs from that of the target device.
.
- PLL clock
PLL is emulated by choosing fixed clock. The PLL input clock frequency (fPLLI) is only 0MHz, 4MHz,
and 8MHz. The PLL output clock frequency (fPLL) become 1MHz if the combination between PLL input clock
frequency and setting of PLLDIV is wrong
(e.g. fPLLI =4MHz PLLDIV =1 => fPLL :1MHz)
- Pull-up
There is a time lag (max 185ns) to work pull up register after setting PUx register.
- LCD controller/driver behavior
When executing STOP instruction or an instruction which stops the main system clock (fMAIN) with setting the
main system clock (fMAIN) to an operation clock of LCD controller/driver, LCD controller/driver stops execution
on target device. On the other hand, it continues execution on QB-RL78D1A2.
- LCD
There is a time lag (max 1ms) to change LCD waveform after the LCD function register setting.
R20UT3110EJ0101 Rev.1.01
Nov 28, 2014
Table 4-3. The detection voltage
Target device RL78/D1A
Rising edge Failing edge
2.50V 2.45V
2.61V 2.55V
2.71V 2.65V
2.81V 2.75V
2.92V 2.86V
3.02V 2.96V
3.13V 3.06V
3.75V 3.67V
4.06V 3.98V
.
CHAPTER 4
QB-RL78D1A2
Rising edge Failing edge
2.46V
2.56V
2.66V
2.76V
2.87V
2.97V
3.07V
3.68V
3.99V
CAUTIONS
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