Mallinckrodt Nellcor N-20 Service Manual page 59

9.10.13.4 Control Conditioning Circuit
The CPU generates a 400-µs low-pulse train at a 160 Hz rate on signal DISP_PHASE. Half of U34
takes DISP_PHASE as an input and creates DISP_POL as an 80 Hz 50% duty cycle square wave. A
CPU reset initializes DISP_POL low when any CPU reset occurs so the software knows the initial
state. The other half of U34 is used to synchronize the rising edge of the DISP_DL with the rising
edge of DISP_POL. The CPU brings DISP_LATCH signal high before the rising edge of
DISP_PHASE; this allows the high to be clocked out to DISP_DL on the rising edge of
DISP_PHASE. About 100 µs after the rising edge of DISP_PHASE, the CPU brings DISP_LATCH
low, asynchronously resetting DISP_DL low.
9.10.13.5 Display Driver Control Circuits
U19 and U20 are the display segment driver chips. Each chip has 32 high-voltage outputs and a
display common marked BP (backplane). The display data are input to U19 and U20 by the CPU via a
serial shift register input. U19 and U20 are daisy-chained together, forming a 64-bit serial shift
register. Display data are loaded and shifted down via the DISP_DATA and DISP_CLK signals.
When all 64 bits of the shift register are loaded, a high pulse on DISP_DL updates the display, all 64
bits at the same time. The display is clocked with an 80 Hz 50% duty cycle waveform by signal
DISP_POL. The display cannot be driven by DC voltages or display damage will result. Display
segments are illuminated by creating a 180-degree phase shift between the segment pin and the BP
common pin. Segments are left dark by making the waveform on the segment pin be in phase with the
BP pin. The display has an electroluminescent (EL) backlight, and is driven the same as the display
segments. Connectors JP2, JP3, and JP5 connect the display and EL backlight to the drive electronics.
9.10.13.6 High Voltage Control Circuit
The cold switch circuit performs two basic functions: (1) it allows the CPU to enable and disable the
display high voltage VDISP, and (2) it slows the edge slew rate of the segment drivers as it switches
the high voltage. When the signal DISP_PHASE is low, Q14 is disabled, pulling VDISP low.
Whenever the CPU is powered on, DISP_PHASE is tristated. The base emitter junction of Q12 pulls
DISP_PHASE low, disabling the high voltage. This assures that the high voltage is only enabled to
the display when controlled by the CPU.
The Taliq display is similar to an LCD in that the load of a segment is mainly capacitive. A cold
switch circuit provides a current-limited 70 V to VDISP. R93, R95, Q21, and Q14 do the on/off
switching and current limiting. As the driver chips' output waveforms and DISP_PHASE change
states, the capacitive loads of the display cause VDISP to current limit until the capacitance is fully
charged. This constant output current is integrated into the display capacitive loads, causing a highly
linear rising and falling voltage ramp on VDISP. Because the high voltage to the drive chips (VDISP)
is ramped, the outputs of the driver chips U19 and U20 are also ramped at the same controlled rate.
This design is used to reduce current spikes on the 70 V power supply, and, in addition, reduces the
EMI generated by the display due to the lower slew rates of the high voltage switching signals.
9.10.14 Standard User Controls
The user controls circuit is illustrated in Figure 9-23.
Technical Supplement
9-21