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results. Due to the CPU configuration, the write strobe WR (WRL pin) is only active for low-byte
writes; therefore, both bytes of the external output port must be written to at the same time. The upper
byte of the output port cannot be written to alone, no write strobe and, therefore, no EXOUTEN signal
will be generated.
U30C generates the EPROMs active low enable signal, ROMEN. The active low signals RAMEN
and EXINEN are basically used as EPROM disable signals. When RAMEN or EXINEN or test point
TP71 are low, the output of U30C, ROMEN, is forced high, disabling the ROM. Therefore, the
EPROM is disabled for the range DC00-FFFF and enabled for the 55 Kbyte address range of
0h-DBFF. TP71 is used during board testing to disable the EPROM.
9.10.10 CPU Memory
The CPU memory circuit is illustrated in Figure 9-17.
The memory system external to the CPU consists of an 8 K × 8 static RAM (U14) and a 64 K × 16
EPROM (U15). The EPROM is 16 bits wide to enhance CPU performance. Because RAM is
infrequently accessed, it is only 8 bits wide.
8K X 8 SRAM
U14
A0
10
A0
9
A1
A1
A2
8
A2
A3
7
A3
6
A4
A4
5
A5
A5
A6
4
A6
A7
3
A7
25
A8
A8
A9
24
A9
A10
21
A10
A11
23
A11
2
A12
A12
RAMEN
20
CS1
26
CS2
27
WR
WE
RD
22
OE
TP43
64K X 16 EPROM
U15
A1
24
A0
A2
25
A1
26
A3
A2
A4
27
A3
A5
28
A4
A6
29
A5
30
A7
A6
A8
31
A7
A9
32
A8
35
A10
A9
36
A11
A10
O10
A12
37
A11
O11
A13
38
A12
O12
39
A14
A13
O13
A15
40
A14
O14
41
A15
O15
ROMEN
3
CE
RD
22
OE
2
VCC
VPP
43
VCC
PGM
27C1024L
Figure 9-17: CPU Memory Circuit
11
AD0
D0
12
AD1
D1
13
AD2
D2
15
AD3
D3
16
AD4
D4
17
AD5
D5
18
AD6
D6
19
AD7
D7
VCC
R133
10K
21
AD0
O0
20
AD1
O1
19
AD2
O2
18
AD3
O3
17
AD4
O4
16
AD5
O5
15
AD6
O6
14
AD7
O7
11
AD8
O8
10
AD9
O9
9
AD10
8
AD11
7
AD12
6
AD13
5
AD14
4
AD15
Technical Supplement
9-17
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