Table of Contents
Advertisement
The N-20 CPU is configured as follows:
•
Decoded AD0 and BHE generate separate WR write strobes for the low and high bytes of a word.
The signal WR (pin WRL) is the low-byte write strobe.
•
A standard address latch enable (ALE) is generated and used.
•
HSO pins 4 and 5 are configured as outputs. The HSO is used to generate stable timing control
signals to the SpO 2 analog section, display, and printer.
•
The timer-2 external control pins T2CLK, T2RST, T2U-D, and T2CAPT are disabled via
software and used as standard I/O.
•
The HOLD, HLDA, and BREQ bus accessing is disabled via software and the pins are used as
standard I/O.
•
Pins HSI0 and EXTINT are configured for interrupt input. The CPU receives 2 external
interrupts (signals PR_TACH and PHOTOI).
•
RXD and TXD are configured as a standard asynchronous serial transmitter and receiver for the
serial interface.
•
PWM0, PWM1, and PWM2 pins are configured as pulse width modulator outputs. They are used
to control gains within the SpO 2 analog section.
9.10.9.1 Address Demultiplexing
The address demultiplexing circuit is illustrated in Figure 9-15.
U13 and U33 are transparent latches that latch the address portion of the AD bus data on the falling
edge of ALE; the outputs are always enabled. The outputs of U13 and U33 are always the address
portion of the AD bus.
ADDRESS DEMUX
U13
AD0
2
19
D1
Q1
3
18
AD1
D2
Q2
AD2
4
17
D3
Q3
AD3
5
16
D4
Q4
6
15
AD4
D5
Q5
7
14
AD5
D6
Q6
AD6
8
13
D7
Q7
AD7
9
12
D8
Q8
ALE
11
C
1
OC
TP39
74HC573
R108
10K
U33
AD8
2
19
D1
Q1
3
18
AD9
D2
Q2
AD10
4
17
D3
Q3
AD11
5
16
D4
Q4
AD12
6
15
D5
Q5
7
14
AD13
D6
Q6
AD14
8
13
D7
Q7
AD15
9
12
D8
Q8
11
ALE
C
1
OC
TP40
74HC573
R109
10K
Figure 9-15: Address Demultiplexing Circuit
Technical Supplement
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
9-15
Advertisement
Table of Contents
